Semiconductor device and manufacturing method thereof

• US 11,177,387 B2
• Filed: 12/23/2019
• Issued: 11/16/2021
• Est. Priority Date: 11/30/2015
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chen, I-Sheng, Yeh, Chih Chieh, Wu, Cheng-Hsien
• Primary Examiner(s): Sarkar, Asok K
• Application Number:
  US16/725,572
• Publication Number:
  US 20200135934A1
• Time in Patent Office: 694 Days
• Field of Search: None
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/82385 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/16 including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 29/161 including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/267 in different semiconductor regions , e.g. heterojunctions H01L29/263 takes precedence
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/66772 : Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/6681 : using dummy structures having essentially the same shape as the semiconductor body, e.g. to provide stability
• CPC Class Codes: H01L 29/7848 : the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/7853 : the body having a non-rectangular crossection
• CPC Class Codes: H01L 29/78618 : characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78696 : characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A semiconductor device includes channel layers disposed over a substrate, a source/drain region disposed over the substrate, a gate dielectric layer disposed on and wrapping each of the channel layers, and a gate electrode layer disposed on the gate dielectric layer and wrapping each of the channel layers. Each of the channel layers includes a semiconductor wire made of a first semiconductor material. The semiconductor wire extends into the source/drain region. The semiconductor wire in the source/drain regions is wrapped around by a second semiconductor material.

Claims

1. A gate-all-around semiconductor device including a gate-all-around field effect transistor (GAA FET), the GAA FET comprising:

semiconductor wires disposed and vertically arranged over a substrate, the semiconductor wires having channel regions, source regions and drain regions, respectively;

a gate dielectric layer wrapping around each of the channel regions of the semiconductor wires;

a gate electrode layer disposed on the gate dielectric layer; and

a source epitaxial layer wrapping around each of the source regions of the semiconductor wires and a drain epitaxial layer wrapping around each of the drain regions of the semiconductor wires, wherein;

the semiconductor wires are made of a first semiconductor material and the source epitaxial layer and the drain epitaxial layer are made of a second semiconductor material different from the first semiconductor material, and

a thickness and a width of each of the source regions and each of the drain regions of the semiconductor wires are smaller than a thickness and a width of each of the channel regions of the semiconductor wires.

2. The semiconductor device of claim 1, wherein the first semiconductor material is Si and the second semiconductor material is at least one of SiP, SiCP and SiC.

3. The semiconductor device of claim 1, wherein the first semiconductor material is Si and the second semiconductor material is at least one of SiGe and Ge.

4. The semiconductor device of claim 1, wherein the source epitaxial layer is continuously formed over the source regions of the semiconductor wires, and the drain epitaxial layer is continuously formed over the drain regions of the semiconductor wires.

5. The semiconductor device of claim 1, further comprising:

a fin structure protruding from the substrate, and

an isolation insulating layer disposed over the substrate, in which the fin structure is at least partially embedded,

wherein the semiconductor wires are vertically disposed over the fin structure.

6. The semiconductor device of claim 5, wherein the fin structure and the semiconductor wires are made of a same semiconductor material.

7. The semiconductor device of claim 5, wherein a bottom most semiconductor wire among the semiconductor wires is separated from the fin structure.

8. The semiconductor device of claim 1, further comprising sidewall spacers disposed on opposing sidewalls of the gate electrode layer,

wherein the source epitaxial layer penetrate under one of the sidewall spacers, and the drain epitaxial layer penetrate under another of the sidewall spacers.

9. A semiconductor device, comprising:

first semiconductor wires made of a first semiconductor material and vertically arranged over a substrate, the semiconductor wires having channel regions and source/drain regions, respectively;

second semiconductor wires made of a second semiconductor material different from the first semiconductor material and each disposed between and connecting adjacent ones of the channel regions of the first semiconductor wires, the channel regions of the first semiconductor wires and the second semiconductor wires forming a channel layer;

a gate dielectric layer disposed on the channel layer,

a gate electrode layer disposed on the gate dielectric layer; and

a source/drain epitaxial layer wrapping around each of the source/drain regions of the first semiconductor wires, wherein;

a thickness and a width of each of the source/drain regions of the first semiconductor wires are smaller than a thickness and a width of each of the channel regions of the first semiconductor wires.

10. The semiconductor device of claim 9, wherein in a cross section along direction perpendicular to a source-to-drain direction, a cross sectional area of each of the channel regions of the first semiconductor wires is greater than a cross sectional area of each of the second semiconductor wires.

11. The semiconductor device of claim 9, wherein in a cross section along direction perpendicular to a source-to-drain direction, a width of each of the second semiconductor wires varies.

12. The semiconductor device of claim 11, wherein in a cross section along direction perpendicular to a source-to-drain direction, a width of each of the second semiconductor wires has a minimum width at a center of each of the second semiconductor wires.

13. The semiconductor device of claim 9, wherein the first semiconductor material is made of SiGe or Ge.

14. The semiconductor device of claim 13, wherein the second semiconductor material is made of Si or a Si based compound.

15. The semiconductor device of claim 9, further comprising:

a fin structure protruding from the substrate, and

an isolation insulating layer disposed over the substrate, in which the fin structure is at least partially embedded,

wherein the first and second semiconductor wires are vertically disposed over the fin structure.

16. The semiconductor device of claim 15, wherein the fin structure and the second semiconductor wires are made of a same semiconductor material.

17. The semiconductor device of claim 15, wherein the source/drain epitaxial layer is continuously formed over the source/drain regions of the first semiconductor wires.

18. The semiconductor device of claim 17, wherein the source/drain epitaxial layer is in contact with the fin structure.

19. A semiconductor device, comprising:

first semiconductor wires made of a first semiconductor material and vertically arranged over a substrate, the semiconductor wires having channel regions and source/drain regions, respectively;

second semiconductor wires made of a second semiconductor material different from the first semiconductor material and each disposed between and connecting adjacent ones of the channel regions of the first semiconductor wires, the channel regions of the first semiconductor wires and the second semiconductor wires forming a first channel layer;

third semiconductor wires made of a third semiconductor material, and vertically arranged over the substrate, the third semiconductor wires having channel regions, source regions and drain regions, respectively;

a gate dielectric layer disposed on the channel layer and wrapping around the channel regions of the third semiconductor wires;

a gate electrode layer disposed on the gate dielectric layer and over the channel layer and the channel regions of the third semiconductor wires;

a first source/drain epitaxial layer wrapping around each of the source/drain regions of the first semiconductor wires; and

a second source/drain epitaxial layer wrapping around each of the source/drain regions of the third semiconductor wires, wherein;

a thickness and a width of each of the source/drain regions of the first semiconductor wires are smaller than a thickness and a width of each of the channel regions of the first semiconductor wires, and

a thickness and a width of each of the source/drain regions of the third semiconductor wires are smaller than a thickness and a width of each of the channel regions of the third semiconductor wires.

20. The semiconductor device of claim 19, wherein:

the first semiconductor material is SiGe,

the second semiconductor material is Si,

the third semiconductor material is Si,

the first source/drain epitaxial layer includes Ge or SiGe having a higher Ge concentration than the first semiconductor material, and

the second source/drain epitaxial layer includes SiP, SiCP or SiC.