Apparatuses, methods, and systems for operations in a configurable spatial accelerator

• US 11,200,186 B2
• Filed: 06/30/2018
• Issued: 12/14/2021
• Est. Priority Date: 06/30/2018
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Fleming, Jr., Kermin E., Steely, Jr., Simon C., Glossop, Kent D., Diamond, Mitchell, Keen, Benjamin, Bradford, Dennis, Petrini, Fabrizio, Tannenbaum, Barry, Zhang, Yongzhi
• Primary Examiner(s): Wong, Titus
• Application Number:
  US16/024,854
• Publication Number:
  US 20190042513A1
• Time in Patent Office: 1,263 Days
• Field of Search: 710306
• CPC Class Codes: G06F 13/4027 using bus bridges G06F13/4022 takes precedence
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Systems, methods, and apparatuses relating to operations in a configurable spatial accelerator are described. In one embodiment, a configurable spatial accelerator includes a first processing element that includes a configuration register within the first processing element to store a configuration value that causes the first processing element to perform an operation according to the configuration value, a plurality of input queues, an input controller to control enqueue and dequeue of values into the plurality of input queues according to the configuration value, a plurality of output queues, and an output controller to control enqueue and dequeue of values into the plurality of output queues according to the configuration value.

Claims

1. An apparatus comprising:

a plurality of processing elements;

an interconnect network between the plurality of processing elements to transfer data values between the plurality of processing elements; and

a first processing element of the plurality of processing elements comprising;

operation circuitry,

a configuration register within the first processing element to store a configuration value, separate from the data values, that causes the first processing element to perform a processing operation with the operation circuitry according to the configuration value,

a plurality of input queues,

an input controller to control enqueue and dequeue of the data values into the plurality of input queues according to the configuration value,

a plurality of output queues, and

an output controller to control enqueue and dequeue of the data values into the plurality of output queues according to the configuration value,

wherein one of;

when at least one of the plurality of input queues is not full, the input controller is to send a ready value to an upstream processing element of the plurality of processing elements, and when at least one of a plurality of output queues of the upstream processing element stores a data value, an output controller of the upstream processing element is to send a valid value to the input controller of the first processing element, and the input controller of the first processing element is to enqueue the data value into the at least one of the plurality of input queues from the at least one of the plurality of output queues of the upstream processing element after both the ready value is asserted by the first processing element and the valid value is received from the upstream processing element, or

when at least one of the plurality of output queues stores a data value, the output controller is to send a valid value to a downstream processing element of the plurality of processing elements, and when at least one of a plurality of input queues of the downstream processing element is not full, an input controller of the downstream processing element is to send a ready value to the output controller of the first processing element, and the output controller of the first processing element is to dequeue the data value from the at least one of the plurality of output queues after both the valid value is asserted by the first processing element and the ready value is received from the downstream processing element.

2. The apparatus of claim 1, wherein, when at least one of the plurality of input queues stores a data value, the input controller is to send a not empty value to the operation circuitry of the first processing element to indicate the first processing element is to begin the processing operation on the data value stored in the at least one of the plurality of input queues.

3. The apparatus of claim 1, wherein, when at least one of the plurality of output queues is not full, the output controller is to send a not full value to the operation circuitry of the first processing element to indicate the first processing element is to begin the processing operation on a data value stored in the at least one of the plurality of input queues.

4. The apparatus of claim 1, wherein, when at least one of the plurality of input queues stores a data value, the input controller is to send a not empty value to the operation circuitry of the first processing element and when at least one of the plurality of output queues is not full, the output controller is to send a not full value to the operation circuitry of the first processing element, and the operation circuitry of the first processing element is to begin the processing operation on the data value stored in the at least one of the plurality of input queues after both the not empty value and the not full value are received.

5. The apparatus of claim 1, wherein the one is, when at least one of the plurality of input queues is not full, the input controller is to send the ready value to the upstream processing element of the plurality of processing elements, and when at least one of the plurality of output queues of the upstream processing element stores the data value, the output controller of the upstream processing element is to send the valid value to the input controller of the first processing element, and the input controller of the first processing element is to enqueue the data value into the at least one of the plurality of input queues from the at least one of the plurality of output queues of the upstream processing element after both the ready value is asserted by the first processing element and the valid value is received from the upstream processing element.

6. The apparatus of claim 5, further comprising, when at least one of the plurality of output queues stores the data value, the output controller is to send the valid value to the downstream processing element of the plurality of processing elements, and when at least one of the plurality of input queues of the downstream processing element is not full, the input controller of the downstream processing element is to send the ready value to the output controller of the first processing element, and the output controller of the first processing element is to dequeue the data value from the at least one of the plurality of output queues after both the valid value is asserted by the first processing element and the ready value is received from the downstream processing element.

7. The apparatus of claim 1, wherein the one is, when at least one of the plurality of output queues stores the data value, the output controller is to send the valid value to the downstream processing element of the plurality of processing elements, and when at least one of the plurality of input queues of the downstream processing element is not full, the input controller of the downstream processing element is to send the ready value to the output controller of the first processing element, and the output controller of the first processing element is to dequeue the data value from the at least one of the plurality of output queues after both the valid value is asserted by the first processing element and the ready value is received from the downstream processing element.

22. The apparatus of claim 1, wherein the first processing element only includes storage for a single configuration value.

8. A method comprising:

coupling a plurality of processing elements together by an interconnect network between the plurality of processing elements to transfer data values between the plurality of processing elements;

storing a configuration value, separate from the data values, in a configuration register within a first processing element of the plurality of processing elements that causes operation circuitry of the first processing element to perform a processing operation according to the configuration value;

controlling enqueue and dequeue of the data values into a plurality of input queues of the first processing element according to the configuration value with an input controller in the first processing element; and

controlling enqueue and dequeue of the data values into a plurality of output queues of the first processing element according to the configuration value with an output controller in the first processing element,

wherein one of;

when at least one of the plurality of input queues is not full, the input controller sends a ready value to an upstream processing element of the plurality of processing elements, and when at least one of a plurality of output queues of the upstream processing element stores a data value, an output controller of the upstream processing element sends a valid value to the input controller of the first processing element, and the input controller of the first processing element enqueues the data value into the at least one of the plurality of input queues from the at least one of the plurality of output queues of the upstream processing element after both the ready value is asserted by the first processing element and the valid value is received from the upstream processing element, or

when at least one of the plurality of output queues stores a data value, the output controller sends a valid value to a downstream processing element of the plurality of processing elements, and when at least one of a plurality of input queues of the downstream processing element is not full, an input controller of the downstream processing element sends a ready value to the output controller of the first processing element, and the output controller of the first processing element dequeues the data value from the at least one of the plurality of output queues after both the valid value is asserted by the first processing element and the ready value is received from the downstream processing element.

9. The method of claim 8, wherein, when at least one of the plurality of input queues stores a data value, the input controller sends a not empty value to the operation circuitry of the first processing element to indicate the first processing element is to begin the processing operation on the data value stored in the at least one of the plurality of input queues.

10. The method of claim 8, wherein, when at least one of the plurality of output queues is not full, the output controller sends a not full value to the operation circuitry of the first processing element to indicate the first processing element is to begin the processing operation on a data value stored in the at least one of the plurality of input queues.

11. The method of claim 8, wherein, when at least one of the plurality of input queues stores a data value, the input controller sends a not empty value to the operation circuitry of the first processing element and when at least one of the plurality of output queues is not full, the output controller sends a not full value to the operation circuitry of the first processing element, and the operation circuitry of the first processing element begins the processing operation on the data value stored in the at least one of the plurality of input queues after both the not empty value and the not full value are received.

12. The method of claim 8, wherein the one is, when at least one of the plurality of input queues is not full, the input controller sends the ready value to the upstream processing element of the plurality of processing elements, and when at least one of the plurality of output queues of the upstream processing element stores the data value, the output controller of the upstream processing element sends the valid value to the input controller of the first processing element, and the input controller of the first processing element enqueues the data value into the at least one of the plurality of input queues from the at least one of the plurality of output queues of the upstream processing element after both the ready value is asserted by the first processing element and the valid value is received from the upstream processing element.

13. The method of claim 12, further comprising, when at least one of the plurality of output queues stores the data value, the output controller sends the valid value to the downstream processing element of the plurality of processing elements, and when at least one of the plurality of input queues of the downstream processing element is not full, the input controller of the downstream processing element sends the ready value to the output controller of the first processing element, and the output controller of the first processing element dequeues the data value from the at least one of the plurality of output queues after both the valid value is asserted by the first processing element and the ready value is received from the downstream processing element.

14. The method of claim 8, wherein the one is, when at least one of the plurality of output queues stores the data value, the output controller sends the valid value to the downstream processing element of the plurality of processing elements, and when at least one of the plurality of input queues of the downstream processing element is not full, the input controller of the downstream processing element sends the ready value to the output controller of the first processing element, and the output controller of the first processing element dequeues the data value from the at least one of the plurality of output queues after both the valid value is asserted by the first processing element and the ready value is received from the downstream processing element.

23. The method of claim 8, wherein the first processing element only includes storage for a single configuration value.

15. A processor comprising:

a core with a decoder to decode an instruction into a decoded instruction and an execution unit to execute the decoded instruction to perform a first operation;

a plurality of processing elements;

an interconnect network between the plurality of processing elements to transfer data values between the plurality of processing elements; and

a first processing element of the plurality of processing elements comprising;

operation circuitry,

a configuration register within the first processing element to store a configuration value, separate from the data values, that causes the first processing element to perform a second, processing operation with the operation circuitry according to the configuration value,

a plurality of input queues,

an input controller to control enqueue and dequeue of the data values into the plurality of input queues according to the configuration value,

a plurality of output queues, and

an output controller to control enqueue and dequeue of the data values into the plurality of output queues according to the configuration value,

wherein one of;

when at least one of the plurality of input queues is not full, the input controller is to send a ready value to an upstream processing element of the plurality of processing elements, and when at least one of a plurality of output queues of the upstream processing element stores a data value, an output controller of the upstream processing element is to send a valid value to the input controller of the first processing element, and the input controller of the first processing element is to enqueue the data value into the at least one of the plurality of input queues from the at least one of the plurality of output queues of the upstream processing element after both the ready value is asserted by the first processing element and the valid value is received from the upstream processing element, or

when at least one of the plurality of output queues stores a data value, the output controller is to send a valid value to a downstream processing element of the plurality of processing elements, and when at least one of a plurality of input queues of the downstream processing element is not full, an input controller of the downstream processing element is to send a ready value to the output controller of the first processing element, and the output controller of the first processing element is to dequeue the data value from the at least one of the plurality of output queues after both the valid value is asserted by the first processing element and the ready value is received from the downstream processing element.

16. The processor of claim 15, wherein, when at least one of the plurality of input queues stores a data value, the input controller is to send a not empty value to the operation circuitry of the first processing element to indicate the first processing element is to begin the second, processing operation on the data value stored in the at least one of the plurality of input queues.

17. The processor of claim 15, wherein, when at least one of the plurality of output queues is not full, the output controller is to send a not full value to the operation circuitry of the first processing element to indicate the first processing element is to begin the second, processing operation on a data value stored in the at least one of the plurality of input queues.

18. The processor of claim 15, wherein, when at least one of the plurality of input queues stores a data value, the input controller is to send a not empty value to the operation circuitry of the first processing element and when at least one of the plurality of output queues is not full, the output controller is to send a not full value to the operation circuitry of the first processing element, and the operation circuitry of the first processing element is to begin the second, processing operation on the data value stored in the at least one of the plurality of input queues after both the not empty value and the not full value are received.

19. The processor of claim 15, wherein the one is, when at least one of the plurality of input queues is not full, the input controller is to send the ready value to the upstream processing element of the plurality of processing elements, and when at least one of the plurality of output queues of the upstream processing element stores the data value, the output controller of the upstream processing element is to send the valid value to the input controller of the first processing element, and the input controller of the first processing element is to enqueue the data value into the at least one of the plurality of input queues from the at least one of the plurality of output queues of the upstream processing element after both the ready value is asserted by the first processing element and the valid value is received from the upstream processing element.

20. The processor of claim 19, further comprising, when at least one of the plurality of output queues stores the data value, the output controller is to send the valid value to the downstream processing element of the plurality of processing elements, and when at least one of the plurality of input queues of the downstream processing element is not full, the input controller of the downstream processing element is to send the ready value to the output controller of the first processing element, and the output controller of the first processing element is to dequeue the data value from the at least one of the plurality of output queues after both the valid value is asserted by the first processing element and the ready value is received from the downstream processing element.

21. The processor of claim 15, wherein the one is, when at least one of the plurality of output queues stores the data value, the output controller is to send the valid value to the downstream processing element of the plurality of processing elements, and when at least one of the plurality of input queues of the downstream processing element is not full, the input controller of the downstream processing element is to send the ready value to the output controller of the first processing element, and the output controller of the first processing element is to dequeue the data value from the at least one of the plurality of output queues after both the valid value is asserted by the first processing element and the ready value is received from the downstream processing element.

24. The processor of claim 15, wherein the first processing element only includes storage for a single configuration value.