Techniques for setting a 2-level auto-close timer to access a memory device

• US 11,216,386 B2
• Filed: 09/26/2019
• Issued: 01/04/2022
• Est. Priority Date: 09/26/2019
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Kozhikkottu, Vivek, Chittor, Suresh, Choukse, Esha, Ramasubramanian, Shankar Ganesh
• Primary Examiner(s): Nguyen, Hiep T
• Application Number:
  US16/584,612
• Publication Number:
  US 20200019513A1
• Time in Patent Office: 831 Days
• CPC Class Codes: G06F 11/3037 where the computing system component is a memory, e.g. virtual memory, cache accessing, addressing or allocating within memory systems or architectures G06F12/00; checking stores for correct operation G11C29/00
• CPC Class Codes: G06F 12/0207 with multidimensional access, e.g. row/column, matrix
• CPC Class Codes: G06F 12/0623 for memory modules
• CPC Class Codes: G06F 12/0851 Cache with interleaved addressing
• CPC Class Codes: G06F 12/0895 of parts of caches, e.g. directory or tag array
• CPC Class Codes: G06F 12/1054 the data cache being concurrently physically addressed
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 2212/684 TLB miss handling

Abstract

Techniques for setting a 2-level auto-close timer to access a memory device include examples of setting first and second time values for the 2-level auto-close timer to cause accessed rows to auto-close following a cache line access to a row of a bank of memory devices. For these examples, the cache line access is responsive to a multi-channel address interleaving policy that causes either successive or non-successive cache line accesses to the bank of memory devices.

Claims

1. An apparatus comprising:

an interface of a memory controller to access memory devices via multiple channels; and

circuitry of the memory controller to;

set a first time value for a first level of a 2-level auto-close timer, the first level of the 2-level auto-close timer to cause a row of a bank of first memory devices to auto-close following a first cache line access to the row responsive to a multi-channel address interleave policy that causes successive cache line accesses to the bank of first memory devices via a first channel of the multiple channels; and

set a second time value for a second level of the 2-level auto-close timer, the second level of the 2-level auto-close timer to cause the row to auto-close following a second cache line access to the row responsive to the multi-channel address interleave policy that causes non-successive cache line accesses to the bank of first memory devices via the first channel.

2. The apparatus of claim 1, wherein the multi-channel address interleave policy comprises a 2-channel address interleave policy that includes a first 4-way interleave that maps physical memory addresses of the bank of first memory devices to a first set of four cache lines of a stream of cache lines to the first channel to cause the successive cache line accesses to the bank of first memory devices.

3. The apparatus of claim 2, wherein the circuitry is further to:

monitor cache line accesses for the first set of four cache lines of the stream of cache lines;

determine a moving average inter-arrival time of at least two successive cache line accesses for the first set of four cache lines; and

adjust the first time value for the first level of the 2-level auto-close timer to increase a likelihood of a page hit for a subsequent cache line access to the bank of first memory devices via the first channel.

4. The apparatus of claim 2, wherein the circuitry is further to:

monitor cache line accesses for the first set of four cache lines of the stream of cache lines;

determine a moving average inter-arrival time of at least two successive cache line accesses for the first set of four cache lines; and

adjust the first time value for the first level of the 2-level auto-close timer to decrease a likelihood of a page miss for a subsequent cache line access to the bank of first memory devices via the first channel.

5. The apparatus of claim 2, wherein the 2-channel address interleave policy is to further include:

a second 4-way interleave that maps physical memory addresses of a row of a bank of second memory devices to a next set of four cache lines of the stream of cache lines to a second channel of the multiple channels;

a third 4-way interleave that maps physical memory addresses of the row of the bank of first memory devices to a third set of four cache lines of the stream of cache lines to the first channel; and

to cause the non-successive cache line accesses to the bank of the first memory devices includes the 2-channel address interleave policy to cause an access to a last cache line of the first 4-way interleave and access to a first cache line of the third 4-way interleave.

6. The apparatus of claim 5, wherein the circuitry is further to:

monitor access to the last cache line of the first 4-way interleave and access to the first cache line of the third 4-way interleave;

determine a moving average inter-arrival time of between access to the last cache line and the first cache line; and

adjust the second time value for the second level of the 2-level auto-close timer to increase a likelihood of a page hit for a subsequent cache line access to the bank of first memory devices via the first channel when the subsequent cache line access is preceded by a cache line access to the bank of second memory devices via the second channel.

7. The apparatus of claim 5, wherein the circuitry is further to:

monitor access to the last cache line of the first 4-way interleave and access to the first cache line of the third 4-way interleave;

determine a moving average inter-arrival time of between access to the last cache line and access to the first cache line; and

adjust the second time value for the second level of the 2-level auto-close timer to decrease a likelihood of a page miss for a subsequent cache line access to the bank of the first memory devices via the first channel when the subsequent cache line access is preceded by a cache line access to the bank of second memory devices.

8. The apparatus of claim 5, wherein the bank of first memory devices includes a plurality of first memory die arranged on a first dual in-line memory module (DIMM) and the bank of the second memory devices includes a plurality of second memory die arranged on a second DIMM.

9. The apparatus of claim 1, wherein the first and second cache line accesses are to separately access 64 bytes of data from the row of the bank of first memory devices.

10. The apparatus of claim 1, wherein the bank of first memory devices comprising a plurality of memory die arranged on a dual in-line memory module (DIMM).

11. The apparatus of claim 1, wherein the first memory devices including dynamic random access memory.

12. A method comprising:

setting, by circuitry of a memory controller, a first time value for a first level of a 2-level auto-close timer, the first level of the 2-level auto-close timer to cause a row of a bank of first memory devices to auto-close following a first cache line access to the row responsive to a multi-channel address interleave policy that causes successive cache line accesses to the bank of first memory devices via a first channel coupled with a processor; and

setting a second time value for a second level of the 2-level auto-close timer, the second level of the 2-level auto-close timer to cause the row to auto-close following a second cache line access to the row responsive to the multi-channel address interleave policy that causes non-successive cache line accesses to the bank of first memory devices via the first channel.

13. The method of claim 12, the multi-channel address interleave policy comprises a 2-channel address interleave policy that includes a first 4-way interleave that maps physical memory addresses of the bank of first memory devices to a first set of four cache lines of a stream of cache lines to the first channel to cause the successive cache line accesses to the bank of first memory devices.

14. The method of claim 13, further comprising:

monitoring cache line accesses for the first set of four cache lines of the stream of cache lines;

determining a moving average inter-arrival time of at least two successive cache line accesses for the first set of four cache lines; and

adjusting the first time value for the first level of the 2-level auto-close timer based on the moving average inter-arrival time to increase a likelihood of a page hit or decrease a likelihood for a page miss for a subsequent cache line access to the bank of first memory devices via the first channel.

15. The method of claim 13, comprising the 2-channel address interleave policy to further include:

a second 4-way interleave that maps physical memory addresses of a row of a bank of second memory devices to a next set of four cache lines of the stream of cache lines to a second channel coupled with the processor;

a third 4-way interleave that maps physical memory addresses of the row of the bank of first memory devices to a third set of four cache lines of the stream of cache lines to the first channel; and

to cause the non-successive cache line accesses to the bank of the first memory devices includes the 2-channel address interleave policy to cause an access to a last cache line of the first 4-way interleave and access to a first cache line of the third 4-way interleave.

16. The method of claim 15, further comprising:

monitoring access to the last cache line of the first 4-way interleave and access to the first cache line of the third 4-way interleave;

determining a moving average inter-arrival time of between access to the last cache line and the first cache line; and

adjusting the second time value for the second level of the 2-level auto-close timer based on the moving average inter-arrival time to increase a likelihood of a page hit or decrease a likelihood of a page miss for a subsequent cache line access to the bank of first memory devices via the first channel when the subsequent cache line access is preceded by a cache line access to the bank of second memory devices via the second channel.

17. At least one non-transitory machine readable medium comprising a plurality of instructions that in response to being executed by a system, cause the system to:

set a first time value for a first level of a 2-level auto-close timer, the first level of the 2-level auto-close timer to cause a row of a bank of first memory devices to auto-close following a first cache line access to the row responsive to a multi-channel address interleave policy that causes successive cache line accesses to the bank of first memory devices via a first channel coupled with a processor; and

set a second time value for a second level of the 2-level auto-close timer, the second level of the 2-level auto-close timer to cause the row to auto-close following a second cache line access to the row responsive to the multi-channel address interleave policy that causes non-successive cache line accesses to the bank of first memory devices via the first channel.

18. The at least one non-transitory machine readable medium of claim 17, the multi-channel address interleave policy comprises a 2-channel address interleave policy that includes a first 4-way interleave that maps physical memory addresses of the bank of first memory devices to a first set of four cache lines of a stream of cache lines to the first channel to cause the successive cache line accesses to the bank of first memory devices.

19. The at least one non-transitory machine readable medium of claim 18, further comprising the instructions to cause the system to:

monitor cache line accesses for the first set of four cache lines of the stream of cache lines;

determine a moving average inter-arrival time of at least two successive cache line accesses for the first set of four cache lines; and

adjust the first time value for the first level of the 2-level auto-close timer based on the moving average inter-arrival time to increase a likelihood of a page hit or decrease a likelihood for a page miss for a subsequent cache line access to the bank of first memory devices via the first channel.

20. The at least one non-transitory machine readable medium of claim 18, comprising the 2-channel address interleave policy to further include:

a second 4-way interleave that maps physical memory addresses of a row of a bank of second memory devices to a next set of four cache lines of the stream of cache lines to a second channel coupled with the processor;

a third 4-way interleave that maps physical memory addresses of the row of the bank of first memory devices to a third set of four cache lines of the stream of cache lines to the first channel; and

to cause the non-successive cache line accesses to the bank of the first memory devices includes the 2-channel address interleave policy to cause an access to a last cache line of the first 4-way interleave and access to a first cache line of the third 4-way interleave.

21. The at least one non-transitory machine readable medium of claim 20, further comprising the instructions to cause the system to:

monitor access to the last cache line of the first 4-way interleave and access to the first cache line of the third 4-way interleave;

determine a moving average inter-arrival time of between access to the last cache line and the first cache line; and

adjust the second time value for the second level of the 2-level auto-close timer based on the moving average inter-arrival time to increase a likelihood of a page hit or decrease a likelihood of a page miss for a subsequent cache line access to the bank of first memory devices via the first channel when the subsequent cache line access is preceded by a cache line access to the bank of second memory devices via the second channel.