High performance integrated RF passives using dual lithography process

• US 11,227,825 B2
• Filed: 12/21/2015
• Issued: 01/18/2022
• Est. Priority Date: 12/21/2015
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Elsherbini, Adel A., Manusharow, Mathew J., Bharath, Krishna, Lambert, William J., Sankman, Robert L., Aleksov, Aleksandar, Rawlings, Brandon M., Eid, Feras, Soto Gonzalez, Javier, Jiao, Meizi, Nad, Suddhasattwa, Kamgaing, Telesphor
• Primary Examiner(s): Chen, Xiaoliang
• Application Number:
  US15/773,030
• Publication Number:
  US 20180315690A1
• Time in Patent Office: 2,220 Days
• Field of Search: 174260, 174257, 174258, 174262, 174267, 361793, 361729, 361811, 336107, 336173, 336192, 336200, 336207, 336227, 336223, 333 24 R, 333 32, 333112, 333129, 333174, 333204, 36012339, 36012341, 36012343, 360123, 360 45, 360 46, 36012345, 36012346, 2960301
• CPC Class Codes: H01F 17/0006 Printed inductances printed coils for dynamo-electric machines H02K3/26; printed circuits H05K
• CPC Class Codes: H01F 2027/2809 on stacked layers
• CPC Class Codes: H01F 27/2804 Printed windings
• CPC Class Codes: H01F 27/40 Structural association with built-in electric component, e.g. fuse
• CPC Class Codes: H01F 41/041 Printed circuit coils apparatus or processes for manufacturing printed circuits in general H05K3/00
• CPC Class Codes: H01G 4/33 Thin- or thick-film capacitors thin- or thick-film circuits H01L27/00; capacitors without a potential-jump or surface barrier specially adapted for integrated circuits, details thereof, multistep manufacturing processes therefor H01L28/40
• CPC Class Codes: H01L 21/4857 Multilayer substrates multilayer metallisation on monolayer substrate H01L21/4846
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 2223/6661 for passive devices passive components per se H01L28/00
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 28/00 Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor testing or measuring during manufacture H01L22/00; integration methods H01L21/70; integrated circuits H01L27/00; two-terminal components with a potential-jump or surface barrier H01L29/00; resistors in general H01C; inductors in general H01F; capacitors in general H01G
• CPC Class Codes: H01L 28/10 Inductors
• CPC Class Codes: H01L 28/60 Electrodes

Abstract

Embodiments of the invention include an electrical package and methods of forming the package. In one embodiment, a transformer may be formed in the electrical package. The transformer may include a first conductive loop that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first conductive loop from a second conductive loop that is formed in the package. Additional embodiments of the invention include forming a capacitor formed in the electrical package. For example, the capacitor may include a first capacitor plate that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first capacitor plate form a second capacitor plate that is formed in the package. The thin dielectric spacer material in the transformer and capacitor allow for increased coupling factors and capacitance density in electrical components.

Claims

1. A transformer in an electrical package comprising:

a first dielectric layer;

a first conductive loop over a surface of the first dielectric layer, wherein a first trace forming the first conductive loop has a first width and a bottommost surface;

a dielectric spacer over the first conductive loop;

a second conductive loop over the surface of the dielectric layer, the second conductive loop laterally adjacent to the first conductive loop in a same plane, and the second conductive loop separated from the first conductive loop by the dielectric spacer layer, wherein the first conductive loop is not electrically connected to the second conductive loop, wherein a second trace forming the second conductive loop has a second width that is smaller than the first width, and wherein the second trace has a bottommost surface co-planar with the bottommost surface of the first trace; and

a second dielectric layer, wherein the first conductive loop, the second conductive loop, and the dielectric spacer are within the second dielectric layer.

2. The transformer of claim 1, wherein the second conductive loop is formed inside a perimeter of the first conductive loop.

3. The transformer of claim 1, wherein the dielectric spacer layer has a thickness that is less than 20 μ

m.

4. The transformer of claim 3, wherein the dielectric spacer layer has a thickness that is less than 5 μ

m.

5. The transformer of claim 1, wherein the dielectric spacer includes a cap layer formed over a top surface of the first conductive loop and a sidewall spacer formed over the sidewalls of the first conductive loop.

6. A transformer in an electrical package comprising:

a first dielectric layer;

a first conductive loop over a surface of the first dielectric layer, wherein a first trace forming the first conductive loop has a first width;

a dielectric spacer over the first conductive loop;

a second conductive loop laterally adjacent to the first conductive loop, the second conductive loop separated from the first conductive loop by the dielectric spacer layer, wherein the first conductive loop is not electrically connected to the second conductive loop, and wherein a second trace forming the second conductive loop has a second width that is smaller than the first width, wherein the second conductive loop is formed over the first dielectric layer, and wherein a sidewall surface of the first conductive loop is separated from a sidewall surface of the second conductive loop by the dielectric spacer; and

a second dielectric layer, wherein the first conductive loop, the second conductive loop, and the dielectric spacer are within the second dielectric layer, wherein the dielectric spacer includes a cap layer formed over a top surface of the first conductive loop and a sidewall spacer formed over the sidewalls of the first conductive loop.

7. A transformer formed in an electrical package comprising:

a first dielectric layer;

a first conductive loop formed over a surface of the first dielectric layer;

a dielectric spacer formed over the first conductive loop; and

a second conductive loop separated from the first conductive loop by the dielectric spacer layer, wherein the first conductive loop is not electrically connected to the second conductive loop, wherein the dielectric spacer includes a cap layer formed over a top surface of the first conductive loop and a sidewall spacer formed over the sidewalls of the first conductive loop, and wherein the cap layer is a different material than the sidewall spacer.

8. A method of forming a transformer in an electrical package, comprising:

forming a first conductive loop over a first dielectric layer, wherein a first trace forming the first conductive loop has a first width and a bottommost surface;

forming a dielectric spacer layer over the first conductive loop;

forming a second conductive loop, wherein the first conductive loop is not electrically connected to the second conductive loop, wherein a second trace forming the second conductive loop has a second width that is smaller than the first width, wherein the second trace has a bottommost surface co-planar with the bottommost surface of the first trace, and wherein the second conductive loop is formed laterally adjacent to first conductive loop in a same plane, and wherein forming the second conductive loop comprises;

forming a seed layer over the dielectric spacer layer;

depositing and patterning a photoresist material to form openings above the first conductive loop; and

plating a conductive material in the openings; and

forming a second dielectric layer, wherein the first conductive loop, the second conductive loop, and the dielectric spacer are within the second dielectric layer.

9. The method of claim 8, wherein the dielectric spacer includes a cap layer formed over a top surface of the first conductive loop and a sidewall spacer formed over the sidewalls of the first conductive loop.