Memory controller and memory system

• US 11,249,895 B2
• Filed: 09/03/2019
• Issued: 02/15/2022
• Est. Priority Date: 10/24/2018
• Status: Active Grant

• Current Assignee: TDK Corporation
• Original Assignee: TDK Corporation
• Inventors: Mukaida, Naoki, Takubo, Kenichi
• Primary Examiner(s): Goldschmidt, Craig S
• Application Number:
  US16/558,464
• Publication Number:
  US 20200133837A1
• Time in Patent Office: 896 Days
• CPC Class Codes: G06F 11/1417 Boot up procedures
• CPC Class Codes: G06F 11/201 between storage system components
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0638 Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module address formation of the next microinstruction G06F9/26; masking faults in memories by using spares or by reconfiguring G11C29/70
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 9/4401 Bootstrapping security arrangements therefor G06F21/57
• CPC Class Codes: G06F 9/4403 Processor initialisation

Abstract

A memory controller for preventing the storage area of a flash memory being reduced is provided. The memory controller controlling access to a flash memory based on a command provided from a host system, the memory controller includes: a processor, a RAM (random access memory), and a mask ROM (read only memory) in which a first firmware is written, wherein the memory controller is configured to: perform a search for a second firmware written in the flash memory based on the first firmware at a start-up time; and write a third firmware provided from the host system in the RAM when the second firmware is not found through the search and perform an initialization based on the third firmware written in the RAM.

Claims

1. A memory controller for controlling access to a flash memory based on a command provided from a host system, the memory controller comprising:

a processor;

a RAM (random access memory); and

a mask ROM (read only memory) in which a first firmware is written,

wherein the memory controller is configured to;

perform a search using the first firmware at a start-up time to determine if a second firmware is detected in the flash memory;

retrieve a third firmware from the host system and write the third firmware to the RAM if the second firmware is not detected in the flash memory; and

perform an initialization based on the third firmware written to the RAM,

wherein the first firmware is software which causes the memory controller to perform a process of searching for the second firmware in the flash memory at the start-up time,

wherein the second firmware is software which causes the memory controller to perform a process of controlling access to the flash memory, and is not able to cause the memory controller to initialize the flash memory, and

the third firmware is software which causes the memory controller to initialize the flash memory, and is not able to cause the memory controller to perform the process of controlling access to the flash memory.

2. The memory controller according to claim 1, wherein the memory controller is configured to, if the second firmware is not present in the flash memory,

perform the initialization so as to include a process to designate a storage area for the second firmware in the flash memory and a process to retrieve the second firmware from the host system and write the second firmware to the storage area.

3. The memory controller according to claim 1, wherein the memory controller is configured to:

transmit error information to the host system when the second firmware is not present in the flash memory; and

receive the third firmware from the host system after the memory controller receives a command from the host system to transmit firmware.

4. The memory controller according to claim 2, wherein the memory controller is configured to:

transmit error information to the host system when the second firmware is not present in the flash memory; and

receive the third firmware from the host system after the memory controller receives a command from the host system to transmit firmware.

5. The memory controller according to claim 2, wherein the memory controller is configured to:

start operation based on the second firmware after writing the second firmware to the storage area.

6. The memory controller according to claim 4, wherein the memory controller is configured to:

start operation based on the second firmware after writing the second firmware to the storage area.

7. A memory system comprising:

a flash memory; and

a memory controller configured to control access to the flash memory based on a command provided from a host system,

wherein the memory controller comprises;

a processor;

a RAM (random access memory); and

a mask ROM (read only memory) in which a first firmware is written,

wherein the memory controller is configured to;

perform a search using the first firmware at a start-up time to determine if a second firmware is detected in the flash memory;

retrieve a third firmware from the host system and write the third firmware to the RAM if the second firmware is not detected in the flash memory; and

perform an initialization based on the third firmware written to the RAM,

wherein the first firmware is software which causes the memory controller to perform a process of searching for the second firmware in the flash memory at the start-up time,

wherein the second firmware is software which causes the memory controller to perform a process of controlling access to the flash memory, and is not able to cause the memory controller to initialize the flash memory, and

the third firmware is software which causes the memory controller to initialize the flash memory, and is not able to cause the memory controller to perform the process of controlling access to the flash memory.

8. The memory system according to claim 7, wherein the memory controller is configured to, if the second firmware is not present in the flash memory,

perform the initialization so as to include a process to designate a storage area for the second firmware in the flash memory and a process to retrieve the second firmware from the host system and write the second firmware to the storage area.

9. The memory system according to claim 7, wherein the memory controller is configured to:

transmit error information to the host system when the second firmware is not present in the flash memory; and

receive the third firmware from the host system after the memory controller receives a command from the host system to transmit.

10. The memory system according to claim 8, wherein the memory controller is configured to:

transmit error information to the host system when the second firmware is not present in the flash memory; and

receive the third firmware from the host system after the memory controller receives a command from the host system to transmit firmware.

11. The memory system according to claim 8, wherein the memory controller is configured to:

start operation based on the second firmware after writing the second firmware to the storage area.

12. The memory system according to claim 10, wherein the memory controller is configured to:

start operation based on the second firmware after writing the second firmware to the storage area.