Semiconductor device structures with liners

• US 11,355,607 B2
• Filed: 10/05/2015
• Issued: 06/07/2022
• Est. Priority Date: 06/19/2013
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Larsen, Christopher J., Daycock, David A., Shrotri, Kunal
• Primary Examiner(s): Parker, Kenneth
• Assistant Examiner(s): Le, Long H
• Application Number:
  US14/875,493
• Publication Number:
  US 20160027882A1
• Time in Patent Office: 2,437 Days
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/0228 deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
• CPC Class Codes: H01L 21/02337 treatment by exposure to a gas or vapour
• CPC Class Codes: H01L 21/3085 characterised by their behaviour during the process, e.g. soluble masks, redeposited masks
• CPC Class Codes: H01L 21/3086 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/32139 using masks
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/788 with floating gate H01L29/78391 takes precedence
• CPC Class Codes: H10B 41/00 Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/60 the control gate being a doped region, e.g. single-poly memory cell

Abstract

Methods of forming semiconductor devices, memory cells, and arrays of memory cells include forming a liner on a conductive material and exposing the liner to a radical oxidation process to densify the liner. The densified liner may protect the conductive material from substantial degradation or damage during a subsequent patterning process. A semiconductor device structure, according to embodiments of the disclosure, includes features extending from a substrate and spaced by a trench exposing a portion of a substrate. A liner is disposed on sidewalls of a region of at least one conductive material in each feature. A semiconductor device, according to embodiments of the disclosure, includes memory cells, each comprising a control gate region and a capping region with substantially aligning sidewalls and a charge structure under the control gate region.

Claims

1. A semiconductor device, comprising:

features extending from a material, neighboring features spaced from one another, at least one feature of the features comprising;

a tunnel dielectric material over the material;

a conductive material over the tunnel dielectric material;

a charge block material over the conductive material;

a region of at least one other conductive material over the material;

a capping material over the region of at least one other conductive material; and

a liner directly on sidewalls of the region of at least one other conductive material and directly on sidewalk and a top surface of the capping material, the liner not on sidewalls of the tunnel dielectric material, the conductive material, and the charge block material, a greater thickness of the liner on the sidewalk of the capping material than a thickness of the liner on the sidewalls of the at least one other conductive material, and the liner comprising hydrogen and at least one of an oxide, a nitride, or an oxynitride.

2. The semiconductor device of claim 1, wherein a portion of the liner is directly on the sidewalls of the region of at least one other conductive material and another portion of the liner is directly on the sidewalls of the capping material over the region of the at least one other conductive material.

3. The semiconductor device of claim 2, wherein a distance between neighboring features is smaller between laterally adjacent another portions of the liner directly on the sidewalls of the capping material than between laterally adjacent portions of the liner directly on the sidewalk of the region of the at least one other conductive material.

4. The semiconductor device of claim 1, wherein the liner comprises a densified liner.

5. The semiconductor device of claim 1, wherein the liner comprises at least one of silicon oxide, silicon nitride, or silicon oxynitride.

6. The semiconductor device of claim 1, wherein:

the region of at least one conductive material comprises a region of tungsten; and

the liner comprises the oxide, the oxide comprising silicon oxide.

7. A semiconductor device, comprising:

memory cell structures, at least one memory cell structure of the memory cell structures comprising;

a control gate region comprising a metallic material;

a capping region overlying the control gate region, sidewalls of the control gate region substantially aligned with sidewalls of the capping region, wherein the capping region defines a width substantially equal to a width defined by the control gate region; and

a liner directly on the capping region and directly on the sidewalls of the control gate region, the liner comprising hydrogen and at least one of an oxide, a nitride, or an oxynitride; and

a charge structure under the control gate region, the liner Trot on sidewalk of the charge structure.

8. The semiconductor device of claim 7, wherein the metallic material consists of an elemental metal.

9. The semiconductor device of claim 7, wherein the control gate region comprises at least one region of the metallic material and at least one region of a doped conductive material.

10. The semiconductor device of claim 9, wherein the doped conductive material comprises conductive doped polysilicon.

11. The semiconductor device of claim 9, wherein the at least one region of the metallic material is over the at least one region of the doped conductive material.

12. The semiconductor device of claim 7, wherein the charge structure defines a wider width than the width defined by the control gate region.

13. The semiconductor device of claim 7, wherein:

sidewalls of the control gate region are perpendicular to a surface of a material supporting the memory cell structures; and

sidewalk of the charge structure are angled relative to the surface of the material.

14. The semiconductor device of claim 7, further comprising:

a charge block region between the charge structure and the control gate region; and

a tunnel dielectric region between the charge structure and a material supporting the memory cell structures.

15. The semiconductor device of claim 14, wherein:

the charge block region comprises a dielectric material; and

the tunnel dielectric region comprises silicon dioxide.

16. A semiconductor device comprising an array of memory cell structures, a memory cell structure of the array of memory cell structures comprising:

a control gate region electrically isolated from an underlying charge structure by a region of a dielectric material;

another region of another dielectric material underlying the charge structure and overlying a material;

a capping region over the control gate region; and

a liner directly on sidewalk of the control gate region and directly on sidewalls and an upper surface of the capping region, the liner comprising hydrogen and at least one of an oxide, a nitride, or an oxynitride, the liner not on sidewalls of the charge structure,

the memory cell structure defining a tapering width along a sidewall of the memory cell structure from the material toward the region of the dielectric material underlying the control gate region, and

the memory cell structure defining a substantially consistent width along the sidewall of the memory cell structure from the control gate region to an upper surface of the capping region, the capping region located directly over the control gate region.

17. The semiconductor device of claim 16, wherein the sidewall of the memory cell structure is substantially smooth at least from the control gate region to the upper surface of the capping region.

18. The semiconductor device of claim 16, wherein:

the control gate region comprises;

a doped conductive material over the region of the dielectric material; and

a metallic material over the doped conductive material; and

the control gate region defines the substantially consistent width along the doped conductive material and the metallic material.

19. A semiconductor device, comprising:

features extending from a material, neighboring features spaced from one another, at least one feature of the features comprising;

a tunnel dielectric material over the material;

a conductive material over the tunnel dielectric material;

a charge block material over the conductive material;

a region of at least one other conductive material over the material;

a capping material over the region of at least one other conductive material; and

a liner directly on sidewalls of the region of at least one other conductive material and directly on sidewalls of the capping material, the liner not on sidewalls of the tunnel dielectric material, the conductive material, and the charge block material, the liner comprising hydrogen and at least one of an oxide, a nitride, or an oxynitride, and a thickness of the liner directly on the sidewalls of the capping material greater than a thickness of the liner directly on the sidewalk of the region of at least one other conductive material.