Structure and formation method of semiconductor device with hybrid fins

• US 11,398,476 B2
• Filed: 12/27/2019
• Issued: 07/26/2022
• Est. Priority Date: 05/16/2018
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Ng, Jin-Aun, Chiang, Kuo-Cheng, Chiang, Hung-Li, Chen, Tzu-Chiang, Chen, I-Sheng
• Primary Examiner(s): Landau, Matthew G
• Assistant Examiner(s): Yemelyanov, Dmitriy
• Application Number:
  US16/728,719
• Publication Number:
  US 20200135729A1
• Time in Patent Office: 942 Days
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A structure and a formation method of a semiconductor device are provided. The semiconductor device structure includes a semiconductor substrate and an isolation structure over the semiconductor substrate. The semiconductor device structure also includes a first fin structure over the semiconductor substrate and surrounded by the isolation structure and a stack of nanostructures over the first fin structure. The nanostructures are separated from each other. The semiconductor device structure further includes a second fin structure over the semiconductor substrate. The second fin structure has an embedded portion surrounded by the isolation structure and a protruding portion over the isolation structure. The embedded portion is separated from the protruding portion by a distance.

Claims

1. A semiconductor device structure, comprising:

a semiconductor substrate;

an isolation structure over the semiconductor substrate;

a first fin structure over the semiconductor substrate and surrounded by the isolation structure;

a stack of nanostructures over the first fin structure, wherein the nanostructures are separated from each other;

a second fin structure over the semiconductor substrate, wherein the second fin structure has an embedded portion surrounded by the isolation structure and a protruding portion over the isolation structure, and the embedded portion is separated from the protruding portion by a distance; and

a metal gate stack over the nanostructures, wherein the metal gate stack comprises a gate dielectric layer and a work function layer, and the work function layer is prevented from being between a bottom of the nanostructures and the first fin structure by the gate dielectric layer.

2. The semiconductor device structure as claimed in claim 1, wherein a total height of the stack of the nanostructures is greater than a total height of the first fin structure.

3. The semiconductor device structure as claimed in claim 2, wherein a total height of the protruding portion of the second fin structure is greater than a total height of the embedded portion of the second fin structure.

4. The semiconductor device structure as claimed in claim 3, wherein a total height of the protruding portion of the second fin structure is greater than a total height of the stack of the nanostructures.

5. The semiconductor device structure as claimed in claim 1, wherein a total height of the protruding portion of the second fin structure is greater than a total height of the stack of nanostructures.

6. The semiconductor device structure as claimed in claim 1, wherein the metal gate stack wraps around each of the nanostructures.

7. The semiconductor device structure as claimed in claim 6, wherein a portion of the gate dielectric layer separates the bottom of the nanostructures from the first fin structure.

8. The semiconductor device structure as claimed in claim 1, a portion of the gate dielectric layer is between the embedded portion and the protruding portion.

9. The semiconductor device structure as claimed in claim 8, wherein the portion of the gate dielectric layer has a thickness substantially equal to the distance between the embedded portion and the protruding portion.

13. The semiconductor device structure as claimed in claim 1, wherein the gate dielectric layer wraps around a sidewall and a top of the embedded portion of the second fin structure.

10. A semiconductor device structure, comprising:

a semiconductor substrate;

a stack of nanostructures, wherein the nanostructures are separated from each other;

a fin structure over the semiconductor substrate, wherein a top of the fin structure is at a higher height level than a top of the nanostructures; and

a metal gate stack wrapping around each of the nanostructures and extending across the fin structure, wherein the metal gate stack comprises a gate dielectric layer and a work function layer, and the work function layer is prevented from being between a bottom of the nanostructures and the semiconductor substrate by the gate dielectric layer.

11. The semiconductor device structure as claimed in claim 10, wherein a first portion of the gate dielectric layer is between a bottom of the nanostructures and the semiconductor substrate, and a second portion of the gate dielectric layer is between a bottom of the fin structure and the semiconductor substrate.

12. The semiconductor device structure as claimed in claim 10, further comprising:

an isolation structure over the semiconductor substrate;

a first embedded fin surrounded by the isolation structure and directly below the stack of the nanostructures, wherein a top of the first embedded fin and a bottom of the nanostructures are separated from each other, and a total height of the nanostructures is greater than a total height of the first embedded fin; and

a second embedded fin surrounded by the isolation structure and directly below the fin structure, wherein a top of the second embedded fin and a bottom of the fin structure are separated from each other, and a total height of the fin structure is greater than a total height of the second embedded fin.

14. The semiconductor device structure as claimed in claim 10, wherein the work function layer is prevented from being between a bottom of the fin structure and the semiconductor substrate by the gate dielectric layer.

15. The semiconductor device structure as claimed in claim 10, wherein a first portion of the gate dielectric layer wrapping around the nanostructures is substantially as thick as a second portion of the gate dielectric layer wrapping around the fin structure.

16. A semiconductor device structure, comprising:

a semiconductor substrate;

a stack of nanostructures suspended over the semiconductor substrate, wherein the nanostructures are separated from each other;

a semiconductor structure suspended over the semiconductor substrate, wherein the semiconductor structure is longer than each of the nanostructures; and

a metal gate stack wrapping around the nanostructures, wherein the metal gate stack comprises a gate dielectric layer and a work function layer, and the work function layer is prevented from being between a bottommost surface of the nanostructures and the semiconductor substrate by the gate dielectric layer.

17. The semiconductor device structure as claimed in claim 16, wherein the work function layer is prevented from being between a bottommost surface of the semiconductor structure and the semiconductor substrate by the gate dielectric layer.

18. The semiconductor device structure as claimed in claim 17, wherein the metal gate stack further wraps around the semiconductor structure.

19. The semiconductor device structure as claimed in claim 18, wherein a first portion of the gate dielectric layer is between the semiconductor substrate and the bottommost surface of the nanostructures, and a second portion of the gate dielectric layer is between the semiconductor substrate and a bottommost surface of the semiconductor structure.

20. The semiconductor device structure as claimed in claim 17, wherein a topmost surface of the nanostructures is closer to the semiconductor substrate than a topmost surface of the semiconductor structure.