Spot-solderable leads for semiconductor device packages

• US 11,430,719 B2
• Filed: 06/27/2019
• Issued: 08/30/2022
• Est. Priority Date: 09/09/2016
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Prakuzhy, Manu A., Gurrum, Siva P., Heussner, Daryl R., Wiktor, Stefan W., Pham, Ken
• Primary Examiner(s): Sandvik, Benjamin P
• Application Number:
  US16/455,583
• Publication Number:
  US 20190318983A1
• Time in Patent Office: 1,160 Days
• Field of Search: None
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/49503 characterised by the die pad
• CPC Class Codes: H01L 23/49548 Cross section geometry H01L23/49562 takes precedence
• CPC Class Codes: H01L 23/49558 Insulating layers on lead frames, e.g. bridging members
• CPC Class Codes: H01L 23/49562 for devices being provided for in H01L29/00
• CPC Class Codes: H01L 23/49575 Assemblies of semiconductor devices on lead frames
• CPC Class Codes: H01L 23/49582 Metallic layers on lead frames
• CPC Class Codes: H01L 23/49586 Insulating layers on lead frames
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: H01L 2924/10271 Silicon-germanium [SiGe]
• CPC Class Codes: H01L 2924/1032 III-V
• CPC Class Codes: H01L 2924/10329 Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/1033 Gallium nitride [GaN]
• CPC Class Codes: H01L 2924/1037 II-VI
• CPC Class Codes: H01L 2924/1305 Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/1306 Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H02M 3/158 including plural semiconductor devices as final control devices for a single load

Abstract

A semiconductor device that has at least one semiconductor chip attached to a leadframe made of sheet metal of unencumbered full thickness. The leadframe has leads of a first subset that alternate with leads of a second subset. The leads of the first and second subsets have elongated straight lead portions that are parallel to each other in a planar array. A cover layer of insulating material is located over portions of un-encapsulated lead surfaces. The portions of the leads of the first and second subsets that don'"'"'t have the cover layer have a metallurgical configuration that creates an affinity for solder wetting.

Claims

1. A semiconductor device comprising:

at least one semiconductor chip attached to leads of a leadframe, the leads made of sheet metal of full thickness and the leads arrayed into a first subset that alternate with a second subset, the subsets having elongated straight lead portions that are parallel to each other in a planar array;

a package of polymeric compound covering the leadframe, the planar array of the straight lead portions of the first and the second subsets are located at a surface of the package, and uncovered surfaces of the leads are coplanar with the surface of the package; and

a surface layer having a metallurgical configuration for low surface energy for portions of the uncovered lead surfaces, the low surface energy layer of the leads of the first subset alternate with the low surface energy layer of the leads of the adjacent second subset, the low energy surface layer inhibiting wetting by solder material.

2. The semiconductor device of claim 1 wherein the surface layer is selected from a group of surface metal compounds including compounds with oxygen, nitrogen, carbon, sulfur.

3. The semiconductor device of claim 1 wherein the at least one semiconductor chip is a first and a second power MOS field effect transistor having input and ground connections, the semiconductor chips are assembled on the leadframe and they are encapsulated by the polymeric compound.

4. The semiconductor device of claim 1 wherein the polymeric compound of the package is an epoxy-based molding compound.

5. The semiconductor device of claim 3 wherein the semiconductor device is a Power Block, the leads of the first subset belonging to the input and ground connections of the first and second power MOS field effect transistors, and the leads of the second subset belong to a switch line connection coupled between the first and second power MOS field effect transistors.

6. The semiconductor device of claim 5 wherein boundaries of the elongated straight lead portions of the first subset and the elongated straight lead portions of the adjacent second subset are selected so that a shortest distance from a border of the un-encapsulated surface of a lead of the first subset to a nearest border of the un-encapsulated surface of a lead of the adjacent second subset is the smallest pin spacing allowed by applicable design rules of the semiconductor device.