Logic gate

• US 20010002797A1
• Filed: 12/04/2000
• Published: 06/07/2001
• Est. Priority Date: 06/04/1998
• Status: Active Grant

• Current Assignee: Siemens AG
• Original Assignee: Siemens AG
• Inventors: Nebel, Gerhard
• Granted Patent: US 6,392,440 B2
• Time in Patent Office: Days
• US Class Current: 326/81
• CPC Class Codes: H03K 19/00315 in field-effect transistor circuits

Abstract

The logic gate has at least one input terminal in which a digital input signal is applied having two possible logical signal values and at least one output terminal to output an output signal having a logical signal values. Two different logical voltage levels are allocated to both possible logical signal values of the output signal and a logic circuit is provided between the input and the output terminals. The logic circuit has several switching elements, especially switching transistors, working or produced according to the logical voltage level. The logic circuit is supplied with a supply potential that exceeds the logic voltage level. The logic circuit has at least two switching elements, especially switching transistors, in the output path allocated to the output terminal.

Claims

1. A logic gate, comprising:

an input terminal for receiving an input signal with two possible logic signal values;

an output terminal for outputting an output signal with two possible logic signal values assigned two different logic voltage levels;

a logic circuit connected between said input terminal and said output terminal and supplied by a supply potential exceeding the logic voltage levels;

said logic circuit having a plurality of switching elements configured to operate according to the logic voltage levels, said logic circuit having an output path connected to said output terminal, said output path having at least two switching elements configured to operate according to the logic voltage levels, connected in series, and acting as a voltage divider.

2. The logic gate according to

claim 1

, wherein said switching elements are switching transistors.

3. The logic gate according to

claim 1

, wherein said output path is one of two reciprocally operating output paths with switching elements constructed and operating complementarily with respect to one another.

4. The logic gate according to

claim 1

, wherein said output path is one of two output paths constructed symmetrically with respect to one another and said output terminal forming a point of symmetry thereof.

5. The logic gate according to

claim 1

, wherein said output path is one of two output paths each having a further switching element connected in series with said at least two switching elements.

6. The logic gate according to

claim 1

, wherein said output path is one of two output paths each having a protective diode device for discharging leakage currents from said switching elements.

7. The logic gate according to

claim 1

, wherein the two logic voltage levels are substantially 3.6 volts and substantially 1.4 volts, and the supply potential is substantially 5 volts.

8. The logic gate according to

claim 1

, wherein said switching elements of said logic circuit are CMOS devices rated at 3.3 volt.

9. The logic gate according to

claim 1

, wherein said logic circuit is a circuit selected from the group consisting of a NOT gate, AND gate, NAND gate, OR gate, EXOR gate, NOR gate, and transmission gate.