Integrated circuit provided with means for calibrating an electronic module and method for calibrating an electronic module of an integrated circuit

• US 20010007091A1
• Filed: 12/20/2000
• Published: 07/05/2001
• Est. Priority Date: 12/23/1999
• Status: Active Grant

• Current Assignee: Silicon Storage Technology Incorporated (Microchip Technology Incorporated), EM Microelectronic - Marin SA (The Swatch Group AG)
• Original Assignee: Advanced Technology Materials, Inc. (Entegris Incorporated), EM Microelectronic - Marin SA (The Swatch Group AG)
• Inventors: Walter, Fabrice, Ratajczak, Christophe
• Granted Patent: US 6,691,055 B2
• Time in Patent Office: Days
• US Class Current: 702/107
• CPC Class Codes: G01R 31/31702 Testing digital circuits including elements other than semiconductor transistors, e.g. biochips, nanofabrics, mems, chips with magnetic elements
• CPC Class Codes: G06F 11/006 Identification G06F11/2289 takes precedence

Abstract

The integrated circuit (1) is provided with integrated calibrating means in order to be able to calibrate at least one electronic module (9) supplying at its output a reference voltage or a time base signal or a reference frequency signal. Said calibrating means are defined by a microcontroller which receives via an input pad (2) of the integrated circuit (1) an external reference signal (3) which is compared to an internal reference signal of the reference module in order to be able to calibrate in an autonomous manner the integrated reference electronic module (9) as a function of the external reference signal (3). The final calibrating parameters are permanently stored with an associated signature in a memory (10) so that each time that voltage is subsequently applied to the circuit said final calibrating parameters are automatically applied to the corresponding reference module (9).

Claims

1. An integrated circuit provided with means for calibrating at least one electronic module, wherein said calibrating means are provided to calibrate in an autonomous manner at least one integrated reference electronic module as a function of an external reference signal introduced into the circuit by an input pad of the circuit and to store the final calibrating parameters with an associated signature when the output signal of the reference module is equal to the external reference signal.

2. An integrated circuit according to

claim 1

, wherein the calibrating means include comparing means intended to receive at its inputs the output signal of the reference module and the external reference signal, and to provide at its output a comparison signal, a microprocessor for controlling the calibration of said reference module as a function of the comparison signal received from the comparing means, a first memory including a calculating algorithm connected to the microprocessor to allow it to calculate calibrating parameters as a function of the comparison signal, and a second memory connected to the microprocessor to store the final calibrating parameters of said module as well as a signature associated with said parameters.

3. An integrated circuit according to

claim 2

, wherein the reference module supplies at its output a reference voltage, and wherein the comparing means are a comparator whose two inputs receive the reference voltage from the module to be calibrated and an external reference voltage.

4. An integrated circuit according to

claim 2

, wherein the reference module is an oscillator supplying at its output a reference frequency signal, and wherein the comparing means are a counter two inputs of which receive the reference frequency signal from the oscillator and the external reference frequency.

5. An integrated circuit according to

claim 1

, wherein it includes a first reference module supplying at its output a reference voltage and a second reference module supplying at its output a reference frequency signal, wherein said circuit receives at a first input pad an external reference voltage for calibrating the first reference module, and at a second input pad an external reference frequency signal for calibrating the second reference module.

6. An integrated circuit according to

claim 1

, wherein the reference module supplies at its output a time base signal which is compared in the comparing means of the calibrating means to an external time base signal.

7. An integrated circuit according to

claim 2

, wherein the first memory is a ROM memory, in that the second memory is an EEPROM memory, and in that a data register is placed as an interface at the input of the reference module to receive the calibrating parameters.

8. A method for calibrating in test phase at least one integrated reference electronic module of at least one integrated circuit according to

claim 1

, wherein it includes the steps of:

a) powering the integrated circuit via an external electric power source;

b) applying on one of the input pads of the integrated circuit an external reference signal in conjunction with calibrating means of the integrated circuit so that they calibrate autonomously by iterating the reference electronic module using calibrating parameters until the reference output signal of the reference module is equal to the external reference signal; and

c) storing the final calibrating parameters provided by the calibrating means and a signature associated with said parameters in memory means.

9. A method according to

claim 8

, wherein, at step b) in the calibrating means, the external reference signal is compared with the output signal of the reference module in comparing means, wherein the calibrating parameters are calculated in a microprocessor as a function of the output signal of the comparing means and on the basis of a calculating algorithm of a first memory connected to the microprocessor, wherein the calibrating parameters are applied to the reference module to modify its reference output signal, wherein the preceding operations are repeated until the reference signal of the module is equal to the external reference signal, and wherein the final calibrating parameters are permanently stored from the microprocessor in a second memory corresponding to the memory means with a signature associated with the final parameters so that each time that voltage is applied to said circuit the second memory automatically provides the microprocessor with the final calibrating parameters to be applied to the reference module so that it provides a calibrated internal reference signal.

10. A calibrating method according to

claim 8

, wherein several integrated circuits of a same semiconductor substrate are supplied with voltage and are calibrated autonomously at the same time using a same external reference signal applied to the corresponding input pad of each circuit in test phase.

11. A calibrating method according to

claim 10

, wherein the probes of a multiple probe card of a test machine are placed on the signal input and output pads of at least two neighbouring circuits, preferably four neighbouring integrated circuits, so that they are calibrated autonomously at the same time.

12. A calibration method according to

claim 8

, wherein each integrated circuit includes a first reference module supplying at its output a reference voltage and a second reference module supplying at its output a reference frequency signal, wherein said circuit receives at a first input pad an external reference voltage for calibrating the first reference module and at a second input pad an external reference frequency signal for calibrating the second reference module.

13. A wafer of integrated circuits according to

claim 1

, wherein said integrated circuits are disposed on the wafer in groups of neighbouring and similar circuits which are oriented differently so that the location of their signal input and output pads allow the probes of a probe card of a test machine to be placed on the pads of a group of integrated circuits to be able to test and calibrate all the circuits of the group at the same time.

14. A wafer according to

claim 13

, wherein the group of integrated circuits includes four neighbouring integrated circuits, wherein the circuits are disposed on two parallel lines so as to form a substantially square group, each circuit being rotated with respect to its immediate neighbour by±

90°

so that all the pads are located at the periphery of the group.