Nanolaminated thin film circuitry materials

• US 20010012600A1
• Filed: 02/12/2001
• Published: 08/09/2001
• Est. Priority Date: 10/27/1999
• Status: Active Grant

• Current Assignee: Shipley Company, LLC (Dow, Inc.)
• Original Assignee: Shipley Company, LLC (Dow, Inc.)
• Inventors: Carpenter, Richard W., Lin, Wen-Yi, Hunt, Andrew T.
• Granted Patent: US 6,632,591 B2
• Time in Patent Office: Days
• US Class Current: 430/313
• CPC Class Codes: H05K 1/162 incorporating printed capacitors
• CPC Class Codes: H05K 1/167 incorporating printed resistors
• CPC Class Codes: H05K 2201/0179 Thin film deposited insulating layer, e.g. inorganic layer for printed capacitor
• CPC Class Codes: H05K 2201/0317 Thin film conductor layer; Thin film passive component
• CPC Class Codes: H05K 2201/0355 Metal foils
• CPC Class Codes: H05K 2201/09309 Core having two or more power planes; Capacitive laminate of two power planes
• CPC Class Codes: H05K 2203/0338 Transferring metal or conductive material other than a circuit pattern, e.g. bump, solder, printed component affixing a prefabricated conductor pattern H05K3/20
• CPC Class Codes: H05K 2203/1338 Chemical vapour deposition
• CPC Class Codes: H05K 3/4623 the circuit boards having internal via connections between two or more circuit layers before lamination, e.g. double-sided circuit boards H05K3/462 takes precedence
• CPC Class Codes: Y10T 428/24917 including metal layer

Abstract

Nanolaminates are formed by alternating deposition, e.g., by combustion chemical vapor deposition (CCVD), layers of resistive material and layers of dielectric material. Outer resistive material layers are patterned to form discrete patches of resistive material. Electrical pathways between opposed patches of resistive material on opposite sides of the laminate act as capacitors. Electrical pathways horizontally through resistive material layers, which may be connected by via plated holes, act as resistors.

Claims

1. A multi-layer laminate for forming thin layer capacitors, resistors or combinations thereof, comprising at least two layers of resistive material and a dielectric material layer interposed between said two layers of resistive material.

2. The multi-layer laminate according to

claim 1

wherein said resistive material layers have a thickness of between about 10 and about 250 nanometers and said dielectric layers have a thickness of between about 10 and about 750 nanometers.

3. The multi-layer laminate according to

claim 1

having at least three layers of resistive material alternating with at least two dielectric material layers.

4. The multi-layer laminate according to

claim 1

wherein said resistive material layers have different resistivities.

5. The multi-layer laminate according to

claim 1

having a plurality of plated via holes, each in electrical contact with selected ones of said resistive material layers to provide resistive pathways.

6. The multi-layer laminate according to

claim 1

wherein said resistive material layers comprise platinum that is doped with a dielectric material.

7. The multi-layer laminate according to

claim 6

wherein said dielectric material layer comprises silica.

8. The multi-layer laminate according to

claim 1

wherein said dielectric material layer and said resistive material layers are formed by combustion chemical vapor deposition and/or controlled atmosphere combustion chemical vapor deposition.

9. The multi-layer laminate according to

claim 1

wherein resistive layers on each side of said laminate are patterned to form discrete resistive patches.

10. The multi-layer laminate according to

claim 9

wherein resistive material layer patches on opposite sides of said laminate have electrical connects, whereby capacitance pathways are provided through said laminate structure between opposed resistive material layer patches.

11. The multi-layer laminate according to

claim 1

wherein said at least two resistive material layers are vapor deposited.

12. The multi-layer laminate according to

claim 1

wherein said at least two resistive material layers are screen printed.

13. The multi-layer laminate according to

claim 1

wherein said at least two resistive material layers are in selective areas.

14. A method of forming a structure which provides capacitance electrical pathways and resistance electrical pathways, the method comprising:

depositing on a substrate a first outer layer of resistive material between about 10 and about 250 nanometers thick,

depositing thereon a layer of dielectric material between about 10 and about 750 nanometers thick,

optionally depositing thereon alternating layers of resistive material, each between about 10 and about 250 nanometers thick, and dielectric material layers, each between about 10 and about 750 nanometers thick,

depositing a second outer layer of resistive material between about 10 and about 250 nanometers thick,

patterning said second outer layer of resistive material to form resistive material patches and providing electrical connects to said resistive material patches,

laminating said second outer layer of resistive material to laminate-supportive dielectric material,

removing said substrate from said first outer layer,

patterning said first outer layer of resistive material to form resistive material patches and providing electrical connects to said resistive material patches, resistive material patches on opposed sides of said laminate providing capacitance electrical pathways, and

providing electrical connects so as to form resistance electrically pathways horizontally through a resistive material layer(s) of said laminate.

15. The method of

claim 14

wherein at least three resistive material layers are deposited and at least two dielectric materials are deposited.

16. The method of

claim 14

wherein said electrical connects that form horizontal resistive electrical pathways are plated via holes.

17. A multi-layer laminate for forming thin layer capacitors, resistors or combinations thereof, comprising one layer of resistive material and one layer of dielectric material.

18. The multi-layer laminate according to

claim 17

wherein said layer of dielectric material is a thin film.

19. The multi-layer laminate according to

claim 18

wherein said dielectric material is an oxide.

20. The multi-layer laminate according to

claim 19

wherein said dielectric material is SiO₂.

21. The multi-layer laminate according to

claim 19

wherein said layer of resistive material is screen printed.

22. The multi-layer laminate according to

claim 17

wherein said layer of resistive material is a thin film less than a micron thick.

23. The multi-layer laminate according to

claim 17

wherein said resistive material layer is vapor deposited.

24. The multi-layer laminate according to

claim 17

wherein said resistive material layer is printed.

25. The multi-layer laminate according to

claim 17

wherein said resistive material layer is in selective areas.

26. The multi-layer laminate according to

claim 17

further comprising a layer of conductive material.

27. The multi-layer laminate according to

claim 26

wherein said layer of dielectric material is between said layer of resistive material and said layer of conductive material.

28. A method for forming multiple thin layer electrical pathways having resistors and capacitors in series, the method comprising,

providing a conductive material layer,

depositing on said conductive material layer a dielectric material layer,

producing patches of resistive material on said dielectric material layer, and

patterning said conductive material layer into conductive traces so as to form resistor/capacitor electrical pathways between first and second electrical traces of pairs of electrical traces,

each such resistor/capacitor electrical pathway being from a first conductive trace through said dielectric material layer to one of said resistor patches as a capacitor, through said resistor patch as a resistor, and from said resistor patch through said dielectric material layer to a second conductive trace as a capacitor.

29. The method according to

claim 28

wherein said resistive material layer has a thickness of between about 10 and about 250 nanometers and said dielectric layer has a thickness of between about 10 and about 750 nanometers.

30. The method according to

claim 28

wherein said resistive material layer comprises platinum that is doped with a dielectric material.

31. The method according to

claim 28

wherein said dielectric material layer comprises silica.

32. A structure providing multiple conductor resistive pathways comprising, a layer of circuitry traces providing pairs of first and second circuitry traces, a layer of resistive material patches, and dielectric material interposed between said pairs of circuitry traces and said patches of resistive material, whereby resistor/capacitor electrical pathways are formed between first and second electrical traces of said pairs;

each such pathway being from a first conductive trace through said dielectrical material layer to one of said resistor patches as a capacitor, through said resistor patch as a resistor, and from said resistor patch through said dielectric material layer to a second conductive trace as a capacitor.

33. The method according to

claim 32

wherein said resistive material layer has a thickness of between about 10 and about 250 nanometers and said dielectric layer has a thickness of between about 10 and about 750 nanometers.

34. The method according to

claim 32

wherein said resistive material layer comprises platinum that is doped with a dielectric material.

35. The method according to

claim 32

wherein said dielectric material layer comprises silica.