SOI-structure MIS field-effect transistor and method of manufacturing the same
First Claim
1. A metal insulator semiconductor (MIS) field-effect transistor of a silicon-on-insulator (SOI) structure, comprising:
- a source region;
a drain region;
a body region;
a gate electrode; and
a PN junction portion;
wherein the body region is interposed between the source region and the drain region;
wherein the body region is electrically connected to the gate electrode by the PN junction portion; and
wherein the PN junction portion is disposed in such a manner that when a voltage is applied to the gate electrode, a reverse voltage is applied to the PN junction portion.
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Accused Products
Abstract
A SOI-structure MOS field-effect transistor. In this transistor, agate electrode and a p− region that is a body region are placed into electrical contact by a PN junction portion. An n+-type portion of the PN junction portion is in electrical contact with the gate electrode and a p+-type portion of the PN junction portion is in electrical contact with a p− region. When a positive voltage is applied to the gate electrode, the above configuration ensures that a reverse voltage is applied to the PN junction portion, so that only a small current on the order of the reverse leakage current of the PN junction flows along the path from the gate electrode, to the PN junction portion and the body region, and into the source region.
74 Citations
20 Claims
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1. A metal insulator semiconductor (MIS) field-effect transistor of a silicon-on-insulator (SOI) structure, comprising:
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a source region;
a drain region;
a body region;
a gate electrode; and
a PN junction portion;
wherein the body region is interposed between the source region and the drain region;
wherein the body region is electrically connected to the gate electrode by the PN junction portion; and
wherein the PN junction portion is disposed in such a manner that when a voltage is applied to the gate electrode, a reverse voltage is applied to the PN junction portion. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A method of manufacturing a metal insulator semiconductor (MIS) field-effect transistor of a silicon-on-insulator (SOI) structure, the method comprising the steps of:
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(a) forming a body region in a silicon-on-insulator (SOI) substrate;
(b) forming a gate electrode and also forming an extended portion that is positioned so as to extend from an end portion of the gate electrode;
(c) using the gate electrode and the extended portion as a mask for the implantation of impurities of a first conductivity type into the SOI substrate, wherein a source region and a drain region of the first conductivity type are formed in such a manner that the body region is interposed between the source region and the drain region; and
wherein a first portion of the first conductivity type is formed in the extended portion;
(d) forming a second portion of a second conductivity type connected to the first portion, by implanting impurities of the second conductivity type into the extended portion;
(e) forming an interlayer dielectric to cover the silicon single crystal layer of the SOI substrate;
(f) forming a hole in the interlayer dielectric through which is exposed part of the extended portion and the silicon single crystal layer of the SOI substrate; and
(g) electrically connecting the extended portion to the silicon single crystal layer of the SOI substrate by forming a connecting layer within the hole. - View Dependent Claims (14, 15)
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16. A method of manufacturing a metal insulator semiconductor (MIS) field-effect transistor of a silicon-on-insulator (SOI) structure, the method comprising the steps of:
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(a) forming a body region in a silicon-on-insulator (SOI) substrate;
(b) forming an insulating layer including a gate insulating film on the body region;
(c) forming a hole in the insulating layer through which is exposed part of a silicon single crystal layer of the SOI substrate; and
(d) forming a gate electrode and an extended portion on the insulating layer, wherein the extended portion is positioned to extend from an end portion of the gate electrode, and is electrically connected to the silicon single crystal layer of the SOI substrate by the hole;
(e) using the gate electrode and the extended portion as a mask for the implantation of impurities of a first conductivity type into the SOI substrate;
wherein a source region and a drain region of the first conductivity type are formed in such a manner that the body region is interposed between the source region and the drain region; and
wherein a first portion of the first conductivity type is formed in the extended portion;
(f) forming a second portion of a second conductivity type connected to the first portion, by implanting impurities of the second conductivity type into the extended portion. - View Dependent Claims (17, 18)
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19. A method of manufacturing a metal insulator semiconductor (MIS) field-effect transistor of a silicon-on-insulator (SOI) structure, the method comprising the steps of:
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(a) forming a body region in a silicon-on-insulator (SOI) substrate;
(b) forming a gate electrode; and
(c) using the gate electrode as a mask for the implantation of impurities of a first conductivity type into the SOI substrate, wherein a source region and a drain region of the first conductivity type are formed in such a manner that the body region is interposed between the source region and the drain region; and
wherein a first portion of a first conductivity type is formed in a silicon single crystal layer of the SOI substrate;
(d) forming a second portion of a second conductivity type by implanting impurities of the second conductivity type into the silicon single crystal layer of the SOI substrate, wherein the second portion is connected to the first portion, and is positioned between the first portion and the body region;
(e) forming an interlayer dielectric in such a manner as to cover the silicon single crystal layer of the SOI substrate;
(f) forming a first hole in the interlayer dielectric to expose part of the silicon single crystal layer of the SOI substrate and forming a second hole in the interlayer dielectric to expose part of the gate electrode; and
(g) forming a wiring layer on the interlayer dielectric, wherein the wiring layer is electrically connected to the silicon single crystal layer of the SOI substrate by the first hole; and
wherein the wiring layer is also electrically connected to the gate electrode by the second hole. - View Dependent Claims (20)
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Specification