Method for manufacturing electronic devices comprising non-volatile memory cells and LV transistors with salicided junctions

• US 20010021556A1
• Filed: 04/16/2001
• Published: 09/13/2001
• Est. Priority Date: 09/11/1998
• Status: Active Grant

• Current Assignee: Bruno Vajana, Giovanna Dalla Libera, Matteo Patelmo, Nadia Galbiati
• Original Assignee: Bruno Vajana, Giovanna Dalla Libera, Matteo Patelmo, Nadia Galbiati
• Inventors: Patelmo, Matteo, Vajana, Bruno, Galbiati, Nadia, Libera, Giovanna Dalla
• Granted Patent: US 6,396,101 B2
• Time in Patent Office: Days
• US Class Current: 438/258
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/41 of a memory region comprising a cell select transistor, e.g. NAND

Abstract

A method for manufacturing electronic devices, such as memory cells and LV transistors, with salicided junctions, that includes: depositing an upper layer of polycrystalline silicon; defining the upper layer, obtaining floating gate regions on first areas, LV gate regions on second areas of a substrate, and undefined regions on the first and third areas of the substrate; forming first cell source regions laterally to the floating gate regions; forming LV source and drain regions laterally to the LV gate regions; forming a silicide layer on the LV source and drain regions, on the LV gate regions, and on the undefined portions; defining HV gate regions on the third areas, and selection gate regions on the first areas; forming source regions laterally to the selection gate regions, and source and drain regions laterally to the HV gate regions.

Claims

1. A method for manufacturing electronic devices, comprising memory cells and low voltage (LV) transistors with salicided junctions, comprising:

depositing an upper layer of polycrystalline silicon;

defining said upper layer, obtaining first cell gate regions, LV gate regions, and undefined portions;

forming first cell source and drain regions laterally to said first cell gate regions;

forming LV source and drain regions, laterally to said LV gate regions; and

forming a silicide layer on said LV source and drain regions, on said LV gate regions, and on said undefined portions.

2. The method of

claim 1

, further comprising forming high voltage (HV) transistors, and in that after forming a silicide layer, defining of HV gate regions is carried out.

3. The method of

claim 2

wherein said memory cells are EEPROM cells comprising a selection transistor and a memory transistor, and before depositing an upper layer, the following are carried out:

a) forming first gate oxide regions on first areas of a substrate of monocrystalline silicon;

b) forming floating gate regions on said first gate oxide regions;

c) forming dielectric regions on said floating gate regions;

d) forming second gate oxide regions on second areas of said substrate, and third gate oxide regions on third areas of said substrate;

and further wherein said LV gate regions extend on said second areas and said undefined portions extend on said first and said third areas of said substrate;

and, after forming a salicide layer, the following are carried out of;

e) removing selective portions of said layer of silicide and of said upper layer from above said first and third areas, thereby forming said HV gate regions on said third areas, as well as gate structures of said selection transistor on said first areas; and

f) forming HV source and drain regions in said third areas, adjacent to said HV gate regions, and selection source regions in said first areas, adjacent to said gate structures of said selection transistor.

4. The method of

claim 3

wherein before said forming first gate oxide regions, the step forming continuity regions in said first areas is carried out;

and simultaneously with forming LV source and drain regions, the forming a source region of said memory transistoris carried out;

and forming first cell drain regions laterally to said cell gate regions comprises forming first LV source and drain regions and first cell source regions.

5. The method of

claim 4

wherein said forming first gate oxide regions comprises providing a matrix oxide layer on the entire surface of said substrate;

removing said matrix oxide layer from said first area, apart from matrix oxide portions arranged across said continuity regions; and

growing a tunnel oxide layer, and wherein said forming floating gate regions and dielectric regions comprises;

g) depositing a polycrystalline silicon layer on said tunnel oxide layer;

h) depositing a dielectric layer on said polycrystalline silicon layer; and

i) removing selective portions of said dielectric layer, said polycrystalline silicon layer, and said tunnel oxide layer from above said first areas, thereby said floating gate regions are arranged above the tunnel oxide portions, as well as in part of said matrix oxide portions and of said continuity regions.

6. The method of

claim 5

wherein said substrate has a first conductivity type, and before forming first gate oxide regions, the following are carried out:

first selectively implanting of doping ionic species of a second conductivity type in said first areas of said substrate;

second implanting, separate from first implanting, of doping ionic species of the second conductivity type in said second areas of said substrate not overlaying said first and third areas; and

third implanting, separate from the first two, of doping ionic species of the second conductivity type in said third areas of said substrate.

7. The method of

claim 5

wherein after said defining of said upper layer, and before said forming a silicide layer, the following are carried out:

j) implanting doping ionic species forming said LV LDD regions aligned with said LV gate regions in said second areas, and intermediate cell source regions in said first areas, aligned with said floating gate regions; and

k) forming first and second spacers laterally to said LV gate regions and, respectively, to said floating gate regions and to said undefined regions on said first areas;

and wherein said LV source and drain regions and source regions of said memory transistor are aligned with said first and second spacers.

8. An electronic device comprising an EEPROM cell, including a selection transistor and a memory transistor, formed in and on a substrate with a first conductivity type;

said memory transistor having a cell structure forming a control gate region and a floating gate region, a first conductive region formed in said substrate of semiconductor material with a second conductivity type on a first side of said cell structure, said first conductive region being overlaid by a silicide region;

said selection transistor comprising a selection gate region, a second and a third conductive region with said second conductivity type formed in said substrate, said third conductive region being arranged on a second side of said cell structure of said memory transistor;

said first and third conductive regions are offset with respect to said floating gate region of said memory transistor.

9. The device of

claim 8

, comprising a low voltage transistor having salicided source and drain regions.

10. The device of

claim 8

wherein said silicide regions are arranged on said gate structure and on said control gate region.

11. The device of

claim 10

wherein said floating gate region has a first length;

said control gate region has a second length shorter than said first length;

said spacer elements extend on both sides of said cell structure of said memory transistor; and

said first conductive region is aligned with one of said spacer elements.

12. A method for manufacturing an integrated electronic device, comprising:

forming active regions of high voltage (HV) conductivity and active regions of low voltage (LV) conductivity in a silicon substrate;

forming floating gate regions in a first area of the regions of HV conductivity;

forming LV gate regions on the LV conductivity regions;

forming LV source and drain regions in the LV conductivity regions and first source and first drain regions in the first area of HV conductivity adjacent the floating gate regions;

forming a silicide layer on the LV source, drain, and gate regions and on the regions of HV conductivity;

removing selected areas of the silicide layer from a second area in the regions of HV conductivity to define HV gate regions; and

forming HV source and drain regions adjacent to the HV gate regions.

13. The method of

claim 12

wherein forming floating gate regions comprises:

forming first cell gate oxide regions in a first area of HV conductivity; and

forming floating gate regions with dielectric regions thereon on the first cell gate oxide regions.

14. The method of

claim 13

, wherein forming LV gate, source, and drain regions comprises:

depositing an upper layer of polycrystalline silicone;

defining the upper layer to obtain first cell gate regions, LV gate regions, and undefined portions;

forming first cell source and drain regions laterally to the first cell gate regions;

forming LV source and drain regions laterally to the LV gate regions; and

wherein forming a silicide layer further comprises forming a silicide layer on the undefined portions.

15. The method of

claim 13

, further comprising:

forming continuity regions in the HV conductivity regions prior to forming the floating gate regions; and

forming floating gate regions comprises providing a matrix oxide layer on the entire surface of the silicon substrate;

removing the matrix oxide layer from the first area of the regions of HV conductivity except for matrix oxide portions formed across the continuity regions; and

growing a tunnel oxide layer in the first area of the regions of HV conductivity.

16. The method of

claim 15

wherein forming floating gate regions comprises:

depositing a polycrystalline silicon layer on the tunnel oxide layer;

depositing a dielectric layer on the polycrystalline silicon layer; and

removing selective portions of the dielectric layer, the polycrystalline silicon layer, and the tunnel oxide layer from above the first areas in the regions of HV conductivity such that the floating gate regions are arranged above the tunnel oxide portions and in portions of the matrix oxide portions and the continuity regions.

17. The method of

claim 16

, further comprising prior to forming a silicide layer;

implanting doping ionic species forming LV lightly-doped drain regions aligned with the LV gate regions, and forming intermediate source regions in the first areas aligned with the floating gate regions; and

forming first and second spacers laterally to the LV gate regions and, respectively, to the floating gate regions and to the undefined regions on the first areas; and

further wherein forming the LV source and drain regions comprises forming the LV source and drain regions, with the source regions in the first areas aligned with the first and second spacers.

18. An integrated electronic device, comprising:

a silicon substrate having active regions of LV conductivity and the HV conductivity formed therein, one or more LV transistors formed in the LV conductivity regions, one or more HV transistors formed in the HV conductivity regions, and an EEPROM memory cell formed in the HV conductivity regions;

each LV transistor having LV drain and source regions formed in the silicon substrate and the LV gate region formed on the silicon substrate, with silicide regions arranged on an indirect contact with the LV drain, source and gate regions; and

each HV transistor having HV source and drain regions formed in the silicon substrate that are not overlaid by silicide regions, and an HV gate region formed on the silicon substrate and arranged directly below a silicide region; and

an EEPROM cell, including a selection transistor and a memory transistor formed in the HV conductivity regions, the memory transistor having a cell structure forming a control gate region and a floating gate region, a first conductive region formed in the silicon substrate with a second conductivity type on a first side of the cell structure, the first conductivity region being overlaid by a silicide region;

the selection transistor comprising a selection gate region, a second and third conductive region with second conductivity type formed in the silicon substrate, and a third conductive region being arranged on a second side of the cell structure of the memory transistor, the first and third conductive regions formed offset with respect to the floating gate region of the memory transistor.

19. The device of

claim 18

wherein the silicide regions are formed on the gate structure and on the control gate region.

20. The device of

claim 19

wherein the floating gate region has a first length, the control gate region has a second length shorter than the first length, and the spacer elements extend on both sides of the cell structure of the memory transistor, and the first conductive region is aligned with one of the spacer elements.