Multi-layered gate for a CMOS imager

• US 20010022371A1
• Filed: 04/12/2001
• Published: 09/20/2001
• Est. Priority Date: 06/15/1999
• Status: Active Grant

• Current Assignee: Aptina Imaging Corporation (ON Semiconductor Corporation)
• Original Assignee: Micron Technology, Inc.
• Inventors: Rhodes, Howard E.
• Granted Patent: US 6,617,623 B2
• Time in Patent Office: Days
• US Class Current: 257/290
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 27/14603 Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H01L 27/14645 Colour imagers
• CPC Class Codes: H01L 27/14689 MOS based technologies
• CPC Class Codes: H01L 27/14692 Thin film technologies, e.g. amorphous, poly, micro- or nanocrystalline silicon

Abstract

A multi-layered gate for use in a CMOS or CCD imager formed with a second gate at least partially overlapping it. The multi-layered gate is a complete gate stack having an insulating layer, a conductive layer, an optional silicide layer, and a second insulating layer, and has a second gate formed adjacent to it which has a second conductive layer that extends at least partially over the surface of the multi-layered gate. The multi-layered gate has improved insulation, thereby resulting in fewer shorts between the conductive layers of the two gates. Also disclosed are processes for forming the multi-layered gate and the overlapping gate.

Claims

1. A pixel sensor cell for use in an imaging device, said pixel sensor cell comprising:

a first insulating layer formed on a substrate;

a first gate formed on said first insulating layer, said first gate comprising a first conductive layer on said first insulating layer, a second insulating layer on the first conductive layer, and insulating spacers formed on the sides of said first gate; and

a second gate formed on said first insulating layer, said second gate comprising a second conductive layer formed on said first insulating layer and extending at least partially over said first gate.

2. The pixel sensor cell of

claim 1

, wherein the first insulating layer is a layer of material selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, ON, NO, and ONO.

3. The pixel sensor cell of

claim 1

, wherein the first conductive layer is a layer of doped polysilicon.

4. The pixel sensor cell of

claim 1

, wherein said first gate further comprises a barrier metal layer on the first conductive layer.

5. The pixel sensor cell of

claim 4

, wherein the barrier metal is titanium nitride.

6. The pixel sensor cell of

claim 4

, wherein the barrier metal is tungsten nitride.

7. The pixel sensor cell of

claim 4

, wherein said first gate further comprises a tungsten layer on the barrier metal layer.

8. The pixel sensor cell of

claim 1

, wherein said first gate further comprises a silicide layer on the first conductive layer.

9. The pixel sensor cell of

claim 8

, wherein the silicide layer is a layer of metal silicide selected from the group consisting of titanium silicide, tungsten silicide, molybdenum silicide, tantalum silicide, platinum silicide, palladium silicide, iridium silicide, and cobalt silicide.

10. The pixel sensor cell of

claim 1

, wherein the second insulating layer is a deposited silicon oxide layer.

11. The pixel sensor cell of

claim 1

, wherein the second insulating layer material is silicon nitride.

12. The pixel sensor cell of

claim 1

, wherein the second insulating layer is ON.

13. The pixel sensor cell of

claim 1

, wherein the second insulating layer is NO.

14. The pixel sensor cell of

claim 1

, wherein the second insulating material is ONO.

15. The pixel sensor cell of

claim 1

, wherein the insulating spacers are silicon oxide spacers.

16. The pixel sensor cell of

claim 1

, wherein the insulating spacers are silicon nitride spacers.

17. The pixel sensor cell of

claim 1

, wherein the insulating spacers are silicon oxynitride spacers.

18. The pixel sensor cell of

claim 1

, wherein the insulating spacers are ON spacers.

19. The pixel sensor cell of

claim 1

, wherein the insulating spacers are NO spacers.

20. The pixel sensor cell of

claim 1

, wherein the insulating spacers are ONO spacers.

21. The pixel sensor cell of

claim 1

, wherein the second conductive layer is a layer of doped polysilicon.

22. The pixel sensor cell of

claim 1

, wherein the second conductive layer is a layer of semitransparent conductive material.

23. The pixel sensor cell of

claim 22

, wherein the semitransparent conductive material is tin oxide.

24. The pixel sensor cell of

claim 22

, wherein the semitransparent conductive material is indium tin oxide.

25. The pixel sensor of

claim 22

, wherein the semitransparent conductive material is a layer of doped polysilicon.

26. The pixel sensor cell of

claim 1

, wherein said second gate further comprises a barrier metal layer on the second conductive layer.

27. The pixel sensor of

claim 26

, wherein the barrier metal is titanium nitride.

28. The pixel sensor of

claim 26

, wherein the barrier metal is tungsten nitride.

29. The pixel sensor cell of

claim 26

wherein said second gate further comprises a tungsten layer on the barrier metal layer.

30. The pixel sensor cell of

claim 1

, wherein said second gate further comprises a silicide layer on the second conductive layer.

31. The pixel sensor cell of

claim 1

, wherein the imaging device is a CMOS imager.

32. The pixel sensor cell of

claim 1

, wherein the imaging device is a CCD imager.

33. The pixel sensor cell of

claim 1

, wherein said first gate is a source follower gate, and said second gate is a row select gate.

34. The pixel sensor cell of

claim 1

, wherein said first gate is a row select gate, and said second gate is a source follower gate.

35. The pixel sensor cell of

claim 1

, wherein said first gate is a transfer gate and said second gate is a photogate.

36. The pixel sensor cell of

claim 1

, wherein said first gate is a photogate and sad second gate is a transfer gate.

118. The imager of

claim 17

, wherein said array, said circuit , and said central processing unit are formed on a single substrate.

37. A pixel sensor cell for use in an imaging device, said pixel sensor cell comprising:

a first insulating layer formed on a substrate;

a first gate formed on said first insulating layer, said first gate comprising a first conductive layer on said first insulating layer, a second insulating layer on the first conductive layer, and insulating spacers formed on the sides of said first gate; and

a second gate formed on said second insulating layer, said second gate comprising a second conductive layer formed on said second insulating layer and extending at least partially over said first gate.

38. The pixel sensor cell of

claim 37

, wherein the first insulating layer is a layer selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, ON, NO, and ONO.

39. The pixel sensor cell of

claim 37

, wherein the first conductive layer is a layer of doped polysilicon.

40. The pixel sensor cell of

claim 37

, wherein said first gate further comprises a barrier metal layer on the first conductive layer.

41. The pixel sensor cell of

claim 40

, wherein the barrier metal is titanium nitride.

42. The pixel sensor cell of

claim 40

, wherein the barrier metal is tungsten nitride.

43. The pixel sensor cell of

claim 40

, wherein said first gate further comprises a tungsten layer on the barrier metal layer.

44. The pixel sensor cell of

claim 37

, wherein said first gate further comprises a silicide layer on the first conductive layer.

45. The pixel sensor cell of

claim 44

, wherein the silicide layer is a layer of metal silicide selected from the group consisting of titanium silicide, tungsten silicide, molybdenum silicide, tantalum silicide, platinum silicide, palladium silicide, iridium silicide, and cobalt silicide.

46. The pixel sensor cell of

claim 37

, wherein the second insulating layer is a deposited silicon oxide layer.

47. The pixel sensor cell of

claim 37

, wherein the second insulating layer material is silicon nitride.

48. The pixel sensor cell of

claim 37

, wherein the second insulating layer is ON.

49. The pixel sensor cell of

claim 37

, wherein the second insulating layer is NO.

50. The pixel sensor cell of

claim 37

, wherein the second insulating material is ONO.

51. The pixel sensor cell of

claim 37

, wherein the insulating spacers are silicon oxide spacers.

52. The pixel sensor cell of

claim 37

, wherein the insulating spacers are silicon nitride spacers.

53. The pixel sensor cell of

claim 37

, wherein the insulating spacers are silicon oxynitride spacers.

54. The pixel sensor cell of

claim 37

, wherein the insulating spacers are ON spacers.

55. The pixel sensor cell of

claim 37

, wherein the insulating spacers are NO spacers.

56. The pixel sensor cell of

claim 37

, wherein the insulating spacers are ONO spacers.

57. The pixel sensor cell of

claim 37

, wherein the second conductive layer is a layer of doped polysilicon.

58. The pixel sensor cell of

claim 37

, wherein the second conductive layer is a layer of semitransparent conductive material.

59. The pixel sensor cell of

claim 58

, wherein the semitransparent conductive material is tin oxide.

60. The pixel sensor cell of

claim 58

, wherein the semitransparent conductive material is indium tin oxide.

61. The pixel sensor of

claim 58

, wherein the semitransparent conductive material is a layer of doped polysilicon.

62. The pixel sensor cell of

claim 37

, wherein said second gate further comprises a barrier metal layer on the second conductive layer.

63. The pixel sensor of

claim 62

, wherein the barrier metal is titanium nitride.

64. The pixel sensor of

claim 62

, wherein the barrier metal is tungsten nitride.

65. The pixel sensor cell of

claim 62

wherein said second gate further comprises a tungsten layer on the barrier metal layer.

66. The pixel sensor cell of

claim 37

, wherein said second gate further comprises a silicide layer on the second conductive layer.

67. The pixel sensor cell of

claim 37

, wherein the imaging device is a CMOS imager.

68. The pixel sensor cell of

claim 37

, wherein the imaging device is a CCD imager.

69. The pixel sensor cell of

claim 37

, wherein said first gate is a source follower gate, and said second gate is a row select gate.

70. The pixel sensor cell of

claim 37

, wherein said first gate is a row select gate, and said second gate is a source follower gate.

71. The pixel sensor cell of

claim 37

, wherein said first gate is a transfer gate and said second gate is a photogate.

72. The pixel sensor cell of

claim 37

, wherein said first gate is a photogate and said second gate is a transfer gate.

116. The CMOS imager of

claim 63

, wherein each pixel sensor cell further comprises an output transistor having a gate electrically connected to the floating diffusion region.

73. A pixel sensor cell for use in an imaging device, said pixel sensor cell comprising:

a photosensitive region of a first conductivity type formed in a substrate;

a floating diffusion region of a second conductivity type formed in the substrate and spaced from said photosensitive region;

a first insulating layer formed on the substrate;

a first gate formed on said first insulating layer over said photosensitive region, said first gate comprising a first conductive layer on said first insulating layer, a second insulating layer on the first conductive layer, and insulating spacers formed on the sides of said first gate; and

a second gate formed on said first insulating layer, said second gate comprising a semitransparent conductive layer formed on said first insulating layer and extending at least partially over said first gate.

74. The pixel sensor cell of

claim 73

, wherein the first conductive layer is a layer of doped polysilicon.

75. The pixel sensor cell of

claim 73

, wherein the first conductive layer is a layer of semitransparent conductive material.

76. The pixel sensor cell of

claim 73

, wherein the second insulating layer is a layer of silicon oxide.

77. The pixel sensor cell of

claim 73

, wherein the insulating spacers are spacers selected from the group consisting of silicon oxide spacers, silicon nitride spacers, silicon oxynitride spacers, ON spacers, NO spacers, and ONO spacers.

78. The pixel sensor cell of

claim 73

, wherein the semitransparent conductive material is doped polysilicon.

79. The pixel sensor cell of

claim 73

, wherein the semitransparent conductive material is tin oxide.

80. The pixel sensor cell of

claim 73

, wherein the semitransparent conductive material is indium tin oxide.

81. The pixel sensor cell of

claim 73

, wherein the imaging device is a CMOS imager.

82. The pixel sensor cell of

claim 73

, wherein the imaging device is a CCD imager.

83. The pixel sensor cell of

claim 73

, wherein said second gate further comprises a barrier metal layer on the semitransparent conductive layer.

84. The pixel sensor cell of

claim 83

, wherein the barrier metal is titanium nitride.

85. The pixel sensor of

claim 83

, wherein the barrier metal is tungsten nitride.

86. The pixel sensor cell of

claim 83

, wherein said second gate further comprises a tungsten layer on the barrier metal layer.

87. The pixel sensor cell of

claim 73

, wherein said second gate further comprises a silicide layer on the semitransparent conductive layer.

88. A pixel sensor cell for use in an imaging device, said pixel sensor cell comprising:

a photosensitive region of a first conductivity type formed in a substrate;

a floating diffusion region of a second conductivity type formed in the substrate and spaced from said photosensitive region;

a first insulating layer formed on the substrate;

a first gate formed on said first insulating layer over said photosensitive region, said first gate comprising a first conductive layer on said first insulating layer, a second insulating layer on the first conductive layer, and insulating spacers formed on the sides of said first gate; and

a second gate formed on said second insulating layer, said second gate comprising a semitransparent conductive layer formed on said second insulating layer and extending at least partially over said first gate.

89. The pixel sensor cell of

claim 88

, wherein the first conductive layer is a layer of doped polysilicon.

90. The pixel sensor cell of

claim 88

, wherein the first conductive layer is a layer of semitransparent conductive material.

91. The pixel sensor cell of

claim 88

, wherein the second insulating layer is a layer of silicon oxide.

92. The pixel sensor cell of

claim 88

, wherein the insulating spacers are spacers selected from the group consisting of silicon oxide spacers, silicon nitride spacers, silicon oxynitride spacers, ON spacers, NO spacers, and ONO spacers.

93. The pixel sensor cell of

claim 88

, wherein the semitransparent conductive material is doped polysilicon.

94. The pixel sensor cell of

claim 88

, wherein the semitransparent conductive material is tin oxide.

95. The pixel sensor cell of

claim 88

, wherein the semitransparent conductive material is indium tin oxide.

96. The pixel sensor cell of

claim 88

, wherein the imaging device is a CMOS imager.

97. The pixel sensor cell of

claim 88

, wherein the imaging device is a CCD imager.

98. The pixel sensor cell of

claim 88

, wherein said second gate further comprises a barrier metal layer on the semitransparent conductive layer.

99. The pixel sensor cell of

claim 98

, wherein the barrier metal is titanium nitride.

100. The pixel sensor of

claim 98

, wherein the barrier metal is tungsten nitride.

101. The pixel sensor cell of

claim 98

, wherein said second gate further comprises a tungsten layer on the barrier metal layer.

102. The pixel sensor cell of

claim 88

, wherein said second gate further comprises a silicide layer on the semitransparent conductive layer.

103. A CMOS imager comprising:

an array of pixel sensor cells, each pixel sensor cell having at least two gates, wherein one of said at least two gates is formed to overlap at least partially on another of said at least two gates; and

a circuit electrically connected to receive and process output signals from said array.

104. The CMOS imager of

claim 103

, wherein the photogate is formed to overlap at least partially on the transfer gate.

105. The CMOS imager of

claim 103

, wherein the transfer gate is formed to overlap at least partially on the photogate.

106. The CMOS imager of

claim 103

, wherein the source follower gate is formed to overlap at least partially on the row select gate.

107. The CMOS imager of

claim 103

, wherein the row select gate is formed to overlap at least partially on the source follower gate.

108. A CMOS imager comprising:

an array of pixel sensor cells, wherein each pixel sensor cell has a first gate stack, a second gate formed to overlap at least partially on the first gate stack, and a floating diffusion region; and

a circuit electrically connected to receive and process output signals from said array.

109. The CMOS imager of

claim 108

, wherein the first gate stacks comprise a first insulating layer, and a conductive layer on the first insulating layer.

110. The CMOS imager of

claim 108

, wherein the second gates comprise a second insulating layer, and a second conductive layer on the second insulating layer.

111. The CMOS imager of

claim 108

, wherein the first gate is a transfer gate and the second gate is a photogate.

112. The CMOS imager of

claim 108

, wherein the first gate is a photogate and the second gate is a transfer gate.

113. The CMOS image of

claim 108

, wherein the first gate is a source follower gate, and the second gate is a row select gate.

114. The CMOS imager of

claim 108

, wherein the first gate is a row select gate, and the second gate is a source follower gate.

115. The CMOS imager of

claim 108

, wherein each pixel sensor cell further comprises a reset transistor for periodically resetting a charge level of the floating diffusion region.

117. An imager comprising:

a CMOS imager, said CMOS imager comprising an array of pixel sensor cells formed in a photosensitive region on a substrate, wherein each pixel sensor cell has at least two gates, wherein one of said at least two gates is formed to overlap at least partially on another of said at least two gates, and a circuit formed in said substrate and electrically connected to the array for receiving and processing signals representing an image output by the array and for providing output data representing said image; and

a central processing unit for receiving and processing data representing said image.

119. The imager of

claim 117

, wherein said array and said circuit are formed on a first substrate and said central processing unit is formed on a second substrate.

120. A method of forming a multi-layered gate for use in an imaging device, comprising the steps of:

forming a first insulating layer on a substrate;

forming a first conductive layer over the first insulating layer;

forming a second insulating layer over the first conductive layer;

forming a first gate from the first conductive layer and the second insulating layer;

forming insulating spacers on the sides of the first gate; and

forming a second gate by forming a second conductive layer on the first insulating layer and extending over the first gate.

121. The method of

claim 120

, wherein before said step of forming a second gate, said method further comprises:

forming an oxide layer on the substrate, wherein the second gate is formed by forming a second conductive layer on the oxide layer and extending over the first gate.

122. The method of

claim 120

, wherein said step of forming a first insulating layer comprises thermal oxidation.

123. The method of

claim 120

, wherein said step of forming a first insulating layer comprises deposition.

124. The method of

claim 120

, wherein said step of forming a first insulating layer comprises forming a silicon oxide layer and hardening the silicon oxide layer with a nitrogen treatment.

125. The method of

claim 120

, wherein said step of forming a first conductive layer comprises chemical vapor deposition.

126. The method of

claim 120

, wherein said step of forming a first conductive layer is a physical vapor deposition step.

127. The method of

claim 120

, further comprising forming a metal silicide layer on the first conductive layer prior to the step of forming a first gate.

128. The method of

claim 127

, wherein said step of forming a metal silicide layer comprises chemical vapor deposition.

129. The method of

claim 127

, wherein said step of forming a metal silicide layer further comprises forming a metal layer on the first conductive layer, and annealing the metal layer.

130. The method of

claim 129

, wherein the metal layer is a material selected from the group consisting of titanium, tungsten, molybdenum, tantalum, platinum, palladium, iridium, and cobalt.

131. The method of

claim 129

, wherein said step of forming a metal layer comprises chemical vapor deposition.

132. The method of

claim 129

, wherein said step of forming a metal layer comprises evaporation.

133. The method of

claim 129

, wherein said step of forming a metal layer comprises sputtering.

134. The method of

claim 129

, wherein said annealing step is carried out at a temperature within the range of approximately 300 to 900 degrees Celsius.

135. The method of

claim 127

, wherein said metal silicide layer is a layer selected from the group consisting of tungsten silicide, titanium silicide molybdenum silicide, tantalum suicide, platinum silicide, palladium silicide, iridium silicide, and cobalt silicide.

136. The method of

claim 120

, wherein said step of forming a second insulating layer comprises deposition.

137. The method of

claim 120

, wherein said step of forming a first gate comprises directional etching of the first conductive layer and the second insulating layer.

138. The method of

claim 137

, wherein said directional etching is a reactive ion etch.

139. The method of

claim 120

, wherein said step of forming a second conductive layer comprises chemical vapor deposition.

140. The method of

claim 120

, wherein said step of forming a second gate comprises directional etching of the second conductive layer.

141. The method of

claim 140

, wherein said directional etching is a reactive ion etch.

142. The method of

claim 120

, wherein the first insulating layer is a layer of material selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, ON, NO, and ONO.

144. The method of

claim 120

, wherein the second insulating layer is a layer of material selected from the group consisting of deposited silicon oxide, silicon nitride, NO, ON, and ONO.

145. The method of

claim 120

, wherein the insulating spacers are spacers selected from the group consisting of silicon oxide spacers, silicon nitride spacers, silicon oxynitride spacers, ON spacers, NO spacers, and ONO spacers.

146. The method of

claim 120

, wherein the second conductive layer is a layer of material selected from the group consisting of doped polysilicon, tin oxide, and indium tin oxide.

143. The method of claim 1206, wherein the first conductive layer is a layer of doped polysilicon.

147. A method of forming a multi-layered gate for use in an imaging device, comprising the steps of:

providing a semiconductor substrate having a photosensitive region of a first conductivity type;

forming a first insulating layer on the semiconductor substrate and over the photosensitive region;

forming a first conductive layer over the first insulating layer;

forming a second insulating layer over the first conductive layer;

patterning at least the first conductive layer to form a first gate;

forming an oxide layer over the semiconductor substrate;

forming a second conductive layer over the oxide layer and at least a portion of the first conductive layer;

forming a second gate from the second conductive layer and the oxide layer; and

forming a floating diffusion region of a second conductivity type in the substrate adjacent the first gate on a side of the first gate opposite the second gate.

148. The method of

claim 147

, wherein the first gate is a transfer gate, and the second gate is a photogate.

149. The method of

claim 147

, wherein the first gate is a photogate, and the second gate is a transfer gate.

150. The method of

claim 147

, wherein the first gate is a row select gate, and the second gate is a source follower gate.

151. The method of

claim 147

, wherein the first gate is a source follower gate, and the second gate is a row select gate.

152. The method of

claim 147

, wherein the first conductivity type IS p-type, and the second conductivity type is n-type.

153. The method of

claim 147

, wherein the first conductivity type is n-type, and the second conductivity type is p-type.

154. The method of

claim 147

, wherein said step of forming a first insulating layer comprises thermal oxidation.

155. The method of

claim 147

, wherein said step of forming a first insulating layer comprises deposition.

156. The method of

claim 147

, wherein said step of forming a second insulating layer comprises deposition.

157. The method of

claim 147

, wherein said step of forming a first conductive layer comprises chemical vapor deposition.

158. The method of

claim 147

, wherein said step of forming a second conductive layer comprises chemical vapor deposition.

159. The method of

claim 147

, wherein the first and the second conductive layers are doped polysilicon layers.

160. The method of

claim 147

, wherein the first insulating layer is a layer of material selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, ON, NO, and ONO.

161. The method of

claim 147

, wherein the second insulating layer is a layer deposited silicon oxide or silicon oxide hardened by a nitrogen treatment.

162. The method of

claim 147

, further comprising forming a reset transistor adjacent to the photosensitive region having a doped region of a second conductivity type as a drain, the floating diffusion region being the source of the reset transistor.

163. The method of

claim 147

, further comprising forming an output transistor having a gate electrically connected to the floating diffusion region.

164. A method of forming a stacked photogate for use in an imaging device, comprising the steps of:

providing a semiconductor substrate having a photosensitive region of a first conductivity type;

forming a first insulating layer on the substrate and over the photosensitive region;

forming a first conductive layer over the first insulating layer adjacent to the photosensitive region;

forming a second insulating layer over the first conductive layer;

patterning the first conductive layer and the second insulating layer to form a transfer gate and a reset gate for a reset transistor;

forming insulating spacers on the sides of the transfer gate;

forming a second conductive layer over the photosensitive region and extending over at least a portion of the transfer gate;

forming a floating diffusion region of a second conductivity type between the transfer gate and the reset gate in the substrate, the floating diffusion region being the source of the reset transistor; and

forming a doped region of a second conductivity type adjacent to the reset gate, the doped region being the drain of the reset transistor.

165. The method of

claim 164

, wherein the first conductivity type is p-type, and the second conductivity type is n-type.

166. The method of

claim 164

, wherein the first conductivity type is n-type, and the second conductivity type is p-type.

167. The method of

claim 164

, wherein said step of forming a first insulating layer comprises thermal oxidation.

168. The method of

claim 164

, wherein said step of forming a first insulating layer comprises deposition.

169. The method of

claim 164

, wherein said step of forming a second insulating layer comprises thermal oxidation.

170. The method of

claim 164

, wherein said step of forming a second insulating layer comprises deposition.

171. The method of

claim 164

, wherein said step of forming a second insulating layer comprises forming a silicon oxide layer and hardening the silicon oxide layer by a nitrogen treatment.

172. The method of

claim 164

, wherein said step of forming a first conductive layer comprises chemical vapor deposition.

173. The method of

claim 164

, wherein said step of forming a second conductive layer comprises chemical vapor deposition.

174. The method of

claim 164

, wherein the first and the second conductive layers are doped polysilicon layers.

175. The method of

claim 164

, wherein the first insulating layer is a layer of material selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, ON, NO, and ONO.

176. The method of

claim 164

, further comprising a step of forming a metal silicide layer on the first conductive layer prior to said step of forming a second insulating layer.

177. The method of

claim 176

, wherein said step of forming a metal silicide layer comprises chemical vapor deposition.

178. The method of

claim 176

, wherein said step of forming a metal silicide layer further comprises forming a metal layer on the first conductive layer, and annealing the metal layer at a temperature within the range of approximately 300 to 800 degrees Celsius.

179. The method of

claim 176

, wherein the metal silicide layer is a layer selected from the group consisting of tungsten silicide, titanium silicide, molybdenum silicide, tantalum silicide, platinum silicide, palladium silicide, iridium silicide, and cobalt silicide.

180. The method of

claim 164

, wherein said step of forming a floating diffusion region comprises ion implantation of at least one dopant into the semiconductor substrate.

181. The method of

claim 164

, further comprising forming an output transistor having a gate electrically connected to the floating diffusion region.