Frame shuttering scheme for increased frame rate

• US 20010024238A1
• Filed: 02/22/2001
• Published: 09/27/2001
• Est. Priority Date: 02/22/2000
• Status: Active Grant

• Current Assignee: Aptina Imaging Corporation (ON Semiconductor Corporation)
• Original Assignee: Micron Technology, Inc.
• Inventors: Fossum, Eric R., Barna, Sandor L.
• Granted Patent: US 7,092,021 B2
• Time in Patent Office: Days
• US Class Current: 348/295
• CPC Class Codes: H04N 25/441 by reading contiguous pixels from selected rows or columns of the array, e.g. interlaced scanning
• CPC Class Codes: H04N 25/76 Addressed sensors, e.g. MOS or CMOS sensors

Abstract

Charge is integrated in N>=2 different groups within a frame buffer to form multiple image fields.

Claims

1. An apparatus, comprising:

an array of photoreceptor pixels, each pixel of the array including a photoreceptor part and control part which selects some aspect of an associated photoreceptor pixel for readout; and

a control element, which selects only specified ones of the photoreceptor pixels in a specific row for integration at any given readout time such that at least each two adjacent pixels integrate at different times.

2. An apparatus as in

claim 1

, wherein said only specified ones include only alternate ones of the photoreceptor pixels, to provide two separate image fields respectively from said array.

3. An apparatus as in

claim 1

, wherein said only specified ones include one pixel out of every N pixels in said array, to provide N separate image fields respectively.

4. An apparatus as in

claim 1

, further comprising an image processor, separating said specified groups of photoreceptor pixels into separate image fields, and providing respective outputs indicative of said separate image fields.

5. An apparatus as in

claim 2

, further comprising an image processor, receiving a pixel stream including two interleaved images and operating to separate said two image fields.

6. An apparatus as in

claim 2

, further comprising a readout system, reading out a first image field at a first time to produce a first image, and a second image field at a second time to produce a second image.

7. An apparatus as in

claim 3

, further comprising a readout system, reading out pixels from each row in a specified order in which at least one pixel in each row is skipped between each two read pixels, to read out pixels in the order 0, N, 2N . . . to provide a first image, and 1, N+1, 2N+1 to provide a next image and so one to provide the N images.

8. A method, comprising:

integrating light indicative of a scene being imaged in a plurality of pixels forming an array, said integrating comprising integrating each of said pixels in said array beginning and ending at substantially the same time but in at least two different groups; and

forming at least two different image fields from the at least two different groups.

9. A method as in

claim 8

, wherein said integrating comprises integrating only certain pixels at any time, with at least one non-integrated pixel being between each integrated pixel at any integration time.

10. A method as in

claim 9

, wherein said forming comprises reading alternate pixels to provide two separate image fields.

11. A method as in

claim 9

, wherein said forming comprises reading one of every N pixels to provide N separate image fields.

12. A method as in

claim 9

, wherein said reading reads all pixels, including multiple interleaved images, and further comprising separating said multiple interleaved images.

13. A method as in

claim 9

, wherein said forming reads a single interleaved image at any time.

14. An apparatus, comprising:

an array of active pixel sensors, each including a photoreceptor portion, and a control portion, said control portion enabling activation of said photoreceptors between an integrating state and into a non integrating state, and also enabling transfer of charge from said photoreceptor to an output; and

a controller, controlling said photoreceptors to integrate in a plurality of different periods, such that at least a first group of photoreceptors integrates during a different time than a second group of said photoreceptors.

15. An apparatus as in

claim 14

, wherein said plurality is two.

16. An apparatus as in

claim 14

, wherein said control portion includes a follower buffer transistor, and a selector.

17. An apparatus as in

claim 14

, wherein said controller controls said photoreceptors to produce said charge from each individual group at a time.

18. An apparatus as in

claim 14

, wherein said controller controls said photoreceptors to produce their respective charge in order, and further comprising an image processor which separates a first image field within said photodetectors from a second image field within said photodetectors.