Circuits and methods using vertical, complementary transistors

• US 20010025985A1
• Filed: 06/04/2001
• Published: 10/04/2001
• Est. Priority Date: 02/24/1998
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Noble, Wendell P.
• Granted Patent: US 6,777,744 B2
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 21/823885 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823821
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/7834 with a non-planar structure, e.g. the gate or the source or the drain being non-planar

Abstract

A method and structure for an improved, vertically configured inverter array is provided. The inverter includes a buried gate contact coupling the body regions of a complementary pair of transistors. An electrical contact couples the second source/drain regions of the complementary pair of transistors. The transistors are formed in vertical pillars of single crystalline semiconductor material.

Claims

1. An inverter, comprising:

a first vertically configured transistor extending outwardly from a semiconductor substrate;

a second vertically configured transistor extending outwardly from a semiconductor substrate;

an electrical contact between source/drain regions of the first and second vertically configured transistors to provide an output for the inverter; and

a gate contact, the gate contact interconnecting the vertically configured transistors wherein the gate contact comprises an input to the inverter.

2. The inverter of

claim 1

, wherein:

the first vertically configured transistor comprises a first transistor type having a number of sides and formed within a first vertically configured structure extending outwardly from the substrate, the first transistor having a body region and first and second source/drain regions;

the first transistor further having a gate that is associated with a side of the first transistor; and

the second vertically configured transistor comprises a second transistor type having a number of sides and formed within a second vertically configured structure extending outwardly from the substrate, the second transistor having a body region and first and second source/drain regions, the second transistor further having a gate that is associated with a side of the second transistor.

3. The inverter of

claim 2

, wherein the gate contact interconnects the gates of the first and second transistors.

4. The inverter of

claim 2

, wherein the electrical contact between first and second transistors is a tungsten shunt that interconnects an outer source/drain region of the first and second transistors.

5. The inverter of

claim 2

, wherein the body region and first and second source/drain regions of the second transistor are oppositely doped from the corresponding body region and first and second source/drain regions of the first transistor.

6. An inverter on a semiconductor substrate, comprising:

a first transistor formed in a first pillar of single crystalline semiconductor material that extends outwardly from the substrate, the pillar having a number of sides, the first transistor having a body region and first and second source/drain regions that are vertically aligned, the first transistor further having a gate that is associated with a side of the first transistor;

a second transistor formed in a second pillar of single crystalline semiconductor material that extends outwardly from the substrate having a number of sides, the second transistor having a body region and first and second source/drain regions formed within the second pillar, the second transistor further having a gate that is associated with a side of the second transistor, wherein the transistors comprise a complementary pair;

a gate contact that is in communication with the body regions of both first and second transistors; and

a metal shunt forming an electrical contact between the first and second transistors.

7. The inverter of

claim 6

, wherein the first source/drain region of first transistor comprises a p+ silicon material.

8. The inverter of

claim 6

, wherein the first source/drain region of first transistor comprises n+ silicon material.

9. An inverter array, comprising;

multiple complementary pairs of transistors extending outwardly from a semiconductor substrate and having upper surfaces, each transistor in a pair having a vertically stacked body region and first and second source/drain regions, each transistor further having a gate;

an electrical contact between the second source/drain regions of the transistors in each complementary pair;

a plurality of isolation trenches extending parallel to and separating the multiple complementary pairs of transistors and between each transistor; and

a gate contact for each complementary pair of transistors, wherein the gate contact is shared between the complementary pair of transistors and wherein the gate contact communicates with the body region of each transistor in the complementary pair.

10. The inverter array of

claim 9

, wherein the electrical contact couples the second source/drain regions of the transistors in the complementary pair.

11. The inverter array of

claim 10

, wherein the electrical contact is a tungsten shunt.

12. The inverter array of

claim 11

, wherein the electrical contact further includes an output to other ones of the multiple complementary pairs of transistors.

13. The inverter array of

claim 12

, wherein the gate contact further includes an electrical input adapted to receive electrical input from both external sources as well as other one of the multiple complementary pairs of transistors.

14. The inverter array of

claim 13

, wherein the gate contact is located below the upper surface of the multiple complementary pairs of transistors.

15. An inverter array on a semiconductor substrate, comprising:

multiple complementary pairs of transistors extending outwardly from the substrate having an upper surface, and each transistor in the pair having a vertically stacked body region between first and second source/drain regions;

a gate contact for each complementary pair of transistors, the gate contact coupling to the body region of each transistor in the complementary pair, and wherein the gate contact is below the upper surface of the multiple complementary pairs of transistors;

an electrical input coupling to the gate contact of each complementary pair;

an electrical contact between the complementary transistors in each pair of transistors; and

an electrical output coupling to each electrical contact.

16. The inverter array of

claim 15

, wherein the gate contact couples to other ones of the multiple complementary pairs of transistors.

17. The inverter array of

claim 15

, wherein the electrical output couples to other ones of the multiple complementary pairs of transistors.

18. An integrated logic circuit, comprising:

multiple complementary pairs of transistors extending outwardly from the substrate having an upper surface, and further each transistor includes a vertically stacked body region between first and second source/drain regions;

a gate contact associated with each of the multiple complementary pairs, wherein the gate contact is shared between the complementary transistors, the gate contact coupling to the body region of each transistor in the pair, and wherein the gate contact is below the upper surface of the multiple complementary pairs of transistors, the gate contact providing an input such that each complementary pair of transistors forms an inverter;

an electrical contact between each complementary pair of transistors to provide an output such that each complementary pair of transistors forms an inverter; and

a metallization layer that selectively interconnects the inputs and outputs of the inverters to form a logic circuit that accepts inputs and produces one or more logical outputs.

19. An input/output device, comprising:

a functional circuit having a plurality of components;

a logic device coupled to the functional circuit, the logic device having at least one inverter, the inverter further comprising;

a complementary pair of transistors extending outwardly from a semiconducting substrate, each complementary pair having an upper surface, each transistor in the complementary pair having a vertically stacked body region between first and second source/drain regions, each transistor having a gate;

a gate contact coupling between the body region in the complementary pair of transistors in each pair, wherein the gate contact is below the upper surface of the multiple complementary pairs of transistors, the gate contact having an input for each inverter;

an electrical contact between the second source/drain regions in the complementary pair of transistors in each pair, the electrical contact having an output for the inverter; and

a metallization layer that selectively interconnects the inputs and outputs of the selected inverters in the array to implement the logical function form the functional circuit.

20. A method of fabricating an inverter, the method comprising:

forming a first vertically configured transistor, the first transistor extending outwardly from a semiconductor substrate;

forming a second vertically configured transistor, the second transistor extending outwardly from a semiconductor substrate;

forming an electrical contact between source/drain regions of the first and second vertically configured transistors to provide an output for the inverter; and

forming a gate contact, the gate contact interconnecting the vertically configured transistors wherein the gate contact comprises an input to the inverter.

21. The method of fabricating an inverter of

claim 20

, wherein forming the first vertically configured transistor comprises forming a first transistor having a number of sides, the first transistor having a body region of a first conductivity type and first and second source/drain regions, the first transistor further having a gate that is associated with a side of the first transistor.

22. The method of fabricating an inverter of

claim 21

, wherein forming the second vertically configured transistor comprises forming a second transistor having a number of sides, the second transistor having a body region of a second conductivity type and first and second source/drain regions, the second transistor further having a gate that is associated with a side of the second transistor.

23. The method of fabricating an inverter of

claim 22

, wherein forming a gate contact comprises forming a gate contact that interconnects the gates of the first and second transistors.

24. The method of fabricating an inverter of

claim 23

, wherein forming the electrical contact between the first and second transistor types comprises forming a tungsten shunt that interconnects a second source/drain region of the first transistor with a second source/drain region of the second transistor.

25. A method of fabricating an inverter, comprising:

forming a first transistor in a first pillar of single crystalline semiconductor material that extends outwardly from the substrate, the first pillar having a number of sides, the first transistor having a body region and first and second source/drain regions that are vertically aligned, the first transistor further having a gate that is associated with a side of the first transistor;

forming a second transistor in a second pillar of single crystalline semiconductor material that extends outwardly from the substrate, the second pillar having a number of sides, the second transistor having a body region and first and second source/drain regions that are vertically aligned, the second transistor further having a gate that is associated with a side of the second transistor;

forming a gate contact that communicates with the body regions of both first and second transistors; and

forming a metal contact between the first and second transistor types.

26. The method of fabricating an inverter of

claim 25

, wherein forming the first transistor includes forming a first source/drain region of a first conductivity.

27. The method of fabricating an inverter of

claim 25

, wherein forming the first transistor includes forming a first source/drain region of a second conductivity type.

28. The method of fabricating an inverter of

claim 25

, wherein forming the first and second transistors includes forming the first source/drain region of the first and second transistors on oppositely doped semiconductor material.

29. The method of fabricating an inverter of

claim 25

, wherein forming first and second transistors comprises selectively growing multiple epitaxial layers of differently doped silicon.

30. A method of fabricating an array of inverters, comprising:

forming multiple complementary pairs of transistors extending outwardly from a semiconductor substrate and having upper surfaces, each transistor in a pair having a vertically stacked body region and a first and second source/drain regions, each transistor further having a gate;

forming an electrical contact between the transistors in each complementary pair;

forming a plurality of isolation trenches extending parallel to and between the multiple complementary pairs of transistors; and

forming a gate contact in each complementary pair of transistors, and wherein the gate contact communicates with the body region of each transistor in the pair.

31. The method of fabricating an array of

claim 30

, wherein forming the electrical contact comprises coupling the second source/drain region of the transistors in each pair.

32. The method of fabricating an array of

claim 30

, and comprising interconnecting electrical contacts and gate contacts of selected pairs so that the array of inverters implements a logical function.

33. The method of fabricating an array of

claim 30

, wherein forming a gate contact further includes forming an electrical input, connected to the gate contact, and adapted to receive electrical input from both external sources as well as other ones of the multiple complementary pairs of transistors.

34. The method of fabricating an array of

claim 30

, wherein forming the gate contact comprises forming the gate contact below the upper surface of the multiple complementary pairs of transistors.

35. The method of fabricating an array of

claim 30

, wherein forming the multiple complementary pairs of transistors includes forming each transistor in a pair of oppositely doped pillars.

36. The method of fabricating an array of

claim 30

, wherein forming multiple complementary pairs of transistors comprises selectively growing multiple epitaxial layers of differently doped silicon.

37. The method of fabricating an array of

claim 30

, wherein forming a plurality of isolation trenches comprises selectively etching an orthogonally bisecting pattern parallel to and between the multiple complementary pairs of transistors.

38. A method of fabricating an array, comprising:

forming alternating first source/drain region layers of differently doped semiconductor material extending outwardly from a semiconductor substrate;

forming alternating body region layers of differently doped semiconductor material on the first source/drain region layer;

forming alternating second source/drain region layers of differently doped semiconductor material on the body region layers;

forming a plurality of isolation trenches so as to form isolated pillars of semiconductor material, each including a first source/drain region, a body region and a second source/drain region for a transistor;

forming a gate contact disposed within at least one of the plurality of trenches, wherein the gate contact couples body regions of a complementary pair of transistors; and

connecting the second source/drain regions of the complementary transistors to form an inverter.

39. A method of fabricating an array of inverters, comprising:

implanting ions into a semiconductor substrate in an alternating parallel pattern so as to form alternating bars of differently doped semiconductor material;

selectively growing, upon the alternating bars, multiple epitaxial layers of differently doped silicon in order to create an alternating parallel pattern of differently doped vertically configured silicon material;

forming a plurality of orthogonally bisecting isolation trenches to form a pattern of differently doped vertically configured silicon pillars;

forming electrical contacts between complementary pairs of the differently doped vertically configured silicon pillars; and

forming gate contacts within at least one of the plurality of orthogonally bisecting isolation trenches that interconnects complementary pairs of differently doped vertically configured silicon pillars.