Data carrier having means for synchronization with a received data stream

• US 20010028691A1
• Filed: 02/28/2001
• Published: 10/11/2001
• Est. Priority Date: 03/03/2000
• Status: Active Grant

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: NXP B.V. (NXP Semiconductors NV)
• Inventors: Posch, Martin
• Granted Patent: US 7,039,133 B2
• Time in Patent Office: Days
• US Class Current: 375/340
• CPC Class Codes: G06K 19/0723 the record carrier comprising an arrangement for non-contact communication, e.g. wireless communication circuits on transponder cards, non-contact smart cards or RFIDs
• CPC Class Codes: G06K 7/0008 General problems related to the reading of electronic memory record carriers, independent of its reading method, e.g. power transfer
• CPC Class Codes: H04L 7/042 Detectors therefor, e.g. correlators, state machines digital correlators in general G06F17/15

Abstract

A data carrier (4) adapted to receive data (D) in the form of data blocks, which data blocks include delimiter data (SD) and (ED) and useful data (UD), includes delimiter data detection means (11) adapted to detect delimiter data (SD) and (ED) of a data block and to generate and supply at least one useful data start signal (SOF; SOFA, SOFB), in which also after the supply of the useful data start signal (SOF; SOFA) the delimiter data (SD) and (ED) can be re-detected continually and the useful data start signal (SOF; SOFB) can be generated and supplied.

Claims

1. A data carrier (4) having an electric circuit (5),

which includes circuit parts (8, 9, 9A) of at least one interface (6), which circuit parts (8, 9, 9A) are adapted to receive data (D) in the form of data blocks, each data block including delimiter data (SD) and useful data (UD), and

which includes delimiter data detection means (11), which are adapted to detect delimiter data (SD) of a data block and to generate and to supply at least one useful data start signal (SOF;

SOFA, SOFB), which at least one useful data start signal (SOF;

SOFA, SOFB) can be generated and supplied upon detection of the delimiter data (SD), and

which includes data test means (12), which are adapted to test the data (D) for data errors, characterized in that the delimiter data detection means (11) are adapted to continually re-detect the delimiter data (SD) of a data block and to generate and to supply the useful data start signal (SOF;

SOFB) also after the supply of the useful data start signal (SOF;

SOFA).

2. A data carrier (4) as claimed in

claim 1

, characterized in that decision means (21) are provided, which during testing with the aid of the data test means (12) are adapted to decide on the basis of at least one decision criterion (V, V1, V2) whether the re-detection of the delimiter data (SD) can be terminated, and after fulfillment of the decision criterion the delimiter data detection means (11) are adapted to terminate the detection of the delimiter data (SD).

3. A data carrier (4) as claimed in

claim 2

, characterized in that delimiter data counting means (24) are provided, which are adapted to count the re-detected delimiter data (SD) and to supply a delimiter data count (BZ), which delimiter data count (BZ) represents a number of counted re-detected delimiter data (SD), and the decision criterion is formed by the delimiter data count (BZ) represented by the number “

1”

.

4. A data carrier (4) as claimed in

claim 3

, characterized in that the decision means (21) form parts of the delimiter data detection means (11).

5. A data carrier (4) as claimed in

claim 2

, characterized in that useful data pulse counting means (25) are provided, which are adapted to count pulses included in the useful data (UD) and to supply a useful data pulse count (W), which useful data pulse count (W) represents a number of pulses counted, and a first decision criterion (V1) is formed by the useful data pulse count (W) represented by the number “

2”

.

8. A data carrier (4) as claimed in

claim 1

, characterized in that start inhibit means (29) for the data test means (12) are provided, which inhibit means are adapted to receive a data error signal (DE) which can be supplied by the data test means (12), the data error signal (DE) enabling a data error to be signaled during the test of the data for data errors, and in the absence of the data error signal (DE) being adapted to inhibit the start of the test of the data (D) for data errors with the aid of the data test means (12).

9. A data carrier (4) as claimed in

claim 8

, characterized in that the start inhibit means (29) are formed with the aid of supply inhibit means (26) which are adapted to inhibit, in the absence of the data error signal (DE), a useful data start signal (SOF) which can be supplied substantially directly after the test.

10. A data carrier (4) as claimed in

claim 8

, characterized in that the start inhibit means (29) are formed with the aid of parts of the delimiter data detection means (11) and the data test means (12).

11. A data carrier (4) as claimed in

claim 8

, characterized in that the start inhibit means (29) are formed with the aid of reception inhibit means (27) which are adapted to inhibit, in the absence of the data error signal (DE), a useful data start signal (SOF) which can be received substantially directly after the test.

12. A data carrier (4) as claimed in

claim 8

, characterized in that the start inhibit means (29) form parts of the data test means (12).

13. A data carrier (4) as claimed in

claim 1

, characterized in that the circuit takes the form of an integrated circuit.

6. A data carrier (4) as claimed in

claim 6

, characterized in that useful data time measurement means (28) are provided, which when the useful data pulse count (W) is represented by the number “

1”

, is adapted to measure a useful data time interval and to generate a useful data time measurement value, which useful data time measurement value represents the measured useful data time interval, and a second decision criterion (V2) is formed by the useful data pulse count (W) represented by the number “

1” and

by the useful data time measurement value, which represents the measured useful data time interval and which corresponds to a time interval typical of the reception of the delimiter data (SD).

7. A data carrier (4) as claimed in

claim 6

, characterized in that the decision means (21) are formed with the aid of parts of the delimiter data detection means (11).

14. A circuit (5) for a data carrier (4),

which includes circuit parts of at least one interface (6), which circuit parts (8, 9, 9A) are adapted to receive data (D) in the form of data blocks, each data block including delimiter data (SD) and useful data (UD), and

which includes delimiter data detection means (11), which are adapted to detect delimiter data (SD) of a data block and to generate and to supply at least one useful data start signal (SOF;

SOFA, SOFB), which at least one useful data start signal (SOF;

SOFA, SOFB) can be generated and supplied upon detection of the delimiter data (SD), and

which includes data test means (12), which are adapted to test the data (D) for data errors, characterized in that the delimiter data detection means (11) are adapted to continually re-detect the delimiter data (SD) of a data block and to generate and to supply the useful data start signal (SOF;

SOFB) also after the supply of the useful data start signal (SOF;

SOFA).

15. A circuit (5) as claimed in

claim 14

, characterized in that decision means (21) are provided, which during testing with the aid of the data test means (12) are adapted to decide on the basis of at least one decision criterion (V, V1, V2) whether the re-detection of the delimiter data (SD) can be terminated, and after fulfillment of the decision criterion the delimiter data detection means (11) are adapted to terminate the detection of the delimiter data (SD).

16. A circuit (5) as claimed in

claim 15

, characterized in that delimiter data counting means (24) are provided, which are adapted to count the re-detected delimiter data (SD) and to supply a delimiter data count (BZ), which delimiter data count (BZ) represents a number of counted re-detected delimiter data (SD), and the decision criterion is formed by the delimiter data count (BZ) represented by the number “

1”

.

17. A circuit (5) as claimed in

claim 16

, characterized in that the decision means (21) form parts of the delimiter data detection means (11).

18. A circuit (5) as claimed in

claim 15

, characterized in that useful data pulse counting means (25) are provided, which are adapted to count pulses included in the useful data (UD) and to supply a useful data pulse count (W), which useful data pulse count (W) represents a number of pulses counted, and a first decision criterion (V1) is formed by the useful data pulse count (W) represented by the number “

2”

.

19. A circuit (5) as claimed in

claim 18

, characterized in that useful data time measurement means (28) are provided, which when the useful data pulse count (W) is represented by the number “

1”

, is adapted to measure a useful data time interval and to generate a useful data time measurement value, which useful data time measurement value represents the measured useful data time interval, and a second decision criterion (V2) is formed by the useful data pulse count (W) represented by the number “

1” and

by the useful data time measurement value, which represents the measured useful data time interval and which corresponds to a time interval typical of the reception of the delimiter data (SD).

20. A circuit (5) as claimed in

claim 19

, characterized in that the decision means (21) are formed with the aid of parts of the delimiter data detection means (11).

21. A circuit (5) as claimed in

claim 14

, characterized in that start inhibit means (29) for the data test means (12) are provided, which inhibit means are adapted to receive a data error signal (DE) which can be supplied by the data test means (12), the data error signal (DE) enabling a data error to be signaled during the test of the data for data errors, and in the absence of the data error signal (DE) being adapted to inhibit the start of the test of the data (D) for data errors with the aid of the data test means (12).

22. A circuit (5) as claimed in

claim 21

, characterized in that the start inhibit means (29) are formed with the aid of supply inhibit means (26) which are adapted to inhibit, in the absence of the data error signal (DE), a useful data start signal (SOF) which can be supplied substantially directly after the test.

23. A circuit (5) as claimed in

claim 21

, characterized in that the start inhibit means (29) are formed with the aid of parts of the delimiter data detection means (11) and the data test means (12).

24. A circuit (5) as claimed in

claim 14

, characterized in that the start inhibit means (29) are formed with the aid of reception inhibit means (27) which are adapted to inhibit, in the absence of the data error signal (DE), a useful data start signal (SOF) which can be received substantially directly after the test.

25. A circuit (5) as claimed in

claim 21

, characterized in that the start inhibit means (29) form parts of the data test means (12).

26. A circuit (5) as claimed in

claim 14

, characterized in that the circuit takes the form of an integrated circuit.