Anti tamper encapsulation for an integrated circuit

• US 20010033012A1
• Filed: 12/26/2000
• Published: 10/25/2001
• Est. Priority Date: 12/30/1999
• Status: Active Grant

• Current Assignee: Universal Imaging Industries, LLC
• Original Assignee: Fritz Kommerling, Kömmerling, Oliver
• Inventors: Kömmerling, Oliver, Kommerling, Fritz
• Granted Patent: US 7,005,733 B2
• Time in Patent Office: Days
• US Class Current: 257/679
• CPC Class Codes: G06F 21/86 Secure or tamper-resistant housings
• CPC Class Codes: G06F 21/87 by means of encapsulation, e.g. for integrated circuits
• CPC Class Codes: G06K 19/073 Special arrangements for circuits, e.g. for protecting identification code in memory protection against unauthorised use of computer memory G06F12/14
• CPC Class Codes: G06K 19/07372 by detecting tampering with the circuit
• CPC Class Codes: G09C 1/00 Apparatus or methods whereby a given sequence of signs, e.g. an intelligible text, is transformed into an unintelligible sequence of signs by transposing the signs or groups of signs or by replacing them by others according to a predetermined system cryptographic typewriters G09C3/00
• CPC Class Codes: H01L 23/57 Protection from inspection, reverse engineering or tampering
• CPC Class Codes: H01L 23/573 using passive means
• CPC Class Codes: H01L 23/576 using active circuits
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/181 Encapsulation
• CPC Class Codes: H04L 2209/12 Details relating to cryptographic hardware or logic circuitry
• CPC Class Codes: H04L 9/002 Countermeasures against attacks on cryptographic mechanisms network architectures or network communication protocols for protection against malicious traffic H04L63/1441
• CPC Class Codes: H04L 9/06 the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
• CPC Class Codes: H04L 9/0866 involving user or device identifiers, e.g. serial number, physical or biometrical information, DNA, hand-signature or measurable physical characteristics
• CPC Class Codes: Y10S 257/922 with means to prevent inspection of or tampering with an integrated circuit, e.g. "smart card", anti-tamper

Abstract

An integrated circuit device comprising: a circuit which uses encryption; and an encapsulation packaging layer; in which the circuit is responsive to at least one physical parameter of the encapsulation to apply the encryption and/or decryption by reading the key therefrom, so that tampering with the encapsulation to gain access to the circuit causes the encryption and/or decryption to fail.

Claims

1. An integrated circuit device comprising:

a circuit which uses encryption; and

a protective member which reduces access to the circuit;

characterised in that the circuit is responsive to at least one physical parameter of the protective member to apply the encryption and/or decryption, so that tampering with the protective member to gain access to the circuit alters the encryption and/or decryption.

2. A device according to

claim 1

, in which the circuit comprises a memory in which data is stored in encrypted form.

3. A device according to

claim 1

, in which the circuit comprises bus lines for connection to a separate memory device.

4. A device according to

claim 1

, in which the protective member comprises an encapsulation around the circuit.

5. A device according to

claim 1

, in which the circuit comprises an encryptor arranged to apply an encryption and/or decryption algorithm to data.

6. A device according to

claim 5

, in which said encryptor is arranged to use an encryption key, and to the circuit is arranged derive said key from said parameter.

7. A device according to

claim 1

, in which said parameter is an electrical parameter.

8. A device according to

claim 1

, in which said parameter is a magnetic parameter.

9. A device according to

claim 1

, in which said parameter is an optical parameter.

10. A device according to

claim 1

, in which said parameter is a radiation parameter.

11. A device according to

claim 1

, wherein said protective member includes a plurality of particles to which said circuit is responsive, within a matrix material.

12. A device according to

claim 11

, wherein said particles are metallic.

13. A device according to

claim 11

, wherein said particles are radioactive.

14. A device according to

claim 11

, wherein said matrix allows passage of radiation, and said parameter is an optical property affected by said particles.

15. A device according to

claim 14

, in which said particles are radiation-producing.

16. A device according to

claim 14

, in which said particles are radiation-absorbing.

17. A device according to

claim 14

, in which said particles are radiation-scattering.

18. A device according to

claim 1

, wherein said protective member includes at least one decrystalhsed portion of a crystalline solid.

19. A device according to

claim 2

or

3

, in which said memory is read-only, and said circuit comprises a decryptor arranged to apply a decryption algorithm to data read therefrom.

20. A device according to

claim 2

or

3

, in which said memory is writeable, and said circuit comprises an encryptor arranged to apply an encryption algorithm to data to be written thereto.

21. A device according to

claim 2

or

3

, in which said memory comprises at least a first memory and a second memory, and said first memory stores data encryption to be used to decrypt data stored in said second, and said circuit is responsive to the parameter to decrypt the contents of the first memory.

22. A device according to

claim 1

comprising tamper-detection logic, responsive to an attempt to gain access to the circuit to generate a tamper signal.

23. A device according to

claim 1

, in which the circuit is jointly responsive both to said physical parameter and to predetermined secret encryption data to apply the encryption and/or decryption.

24. A device according to

claim 23

, comprising tamper-detection logic, responsive to an attempt to gain access to the circuit to generate a tamper signal.

25. A device according to

claim 24

, in which the circuit is arranged to erase the predetermined secret encryption data in response to the tamper signal.

26. A device according to

claim 1

, further comprising a shield surrounding the protective member, and arranged to reduce the effects of external conditions on the physical parameter.

27. A device according to

claim 1

, further comprising at least one sensor responsive to said protective member, from which said at least one parameter can be derived by said circuit.

28. A device according to

claim 27

comprising a plurality of sensors to sense said at least one physical parameter.

29. A device according to

claim 28

in which said sensors are disposed in an array over at least part of said circuit.

30. A device according to

claim 29

in which the inter-sensor spacing is on the order of a micron.

31. A device according to

claim 28

further comprising a scanning circuit arranged to periodically read said sensors.

32. A device according to

claim 31

, in which said scanning circuit is arranged to vary the order of reading said sensors.

33. A device according to

claim 31

, further comprising a checking circuit arranged to check whether the outputs of said sensors correspond to previous values thereof.

34. An integrated circuit device comprising a memory in which data is stored in encrypted form, and a circuit for applying encryption and/or decryption to write and/or read the data, the circuit comprising a key register storing a key for use in said encryption and/or decryption, and an alternation circuit arranged to vary the data stored in the key register at frequent intervals.

35. A method of accessing encrypted data stored in a memory device, comprising deriving encryption data from a protective member which blocks access to the circuit, and using said encryption data to access said encrypted data.