Hermetic feedthrough for an implantable device

• US 20010039374A1
• Filed: 06/14/2001
• Published: 11/08/2001
• Est. Priority Date: 09/12/1997
• Status: Active Grant

• Current Assignee: Alfred E. Mann Foundation For Scientific Research
• Original Assignee: Alfred E. Mann Foundation For Scientific Research
• Inventors: Schulman, Joseph H.
• Granted Patent: US 6,516,808 B2
• Time in Patent Office: Days
• US Class Current: 600/300
• CPC Class Codes: A61B 2560/0219 of externally powered implanted units
• CPC Class Codes: A61B 5/0031 Implanted circuitry
• CPC Class Codes: A61B 5/01 Measuring temperature of body parts ; Diagnostic temperature sensing, e.g. for malignant or inflamed tissue clinical contact thermometers G01K13/20
• CPC Class Codes: A61B 5/145 Measuring characteristics of blood in vivo, e.g. gas concentration, pH value; Measuring characteristics of body fluids or tissues, e.g. interstitial fluid, cerebral tissuemeasuring of blood pressure or blood flow A61B5/02; non-radiation detecting or locating of foreign bodies in blood A61B5/06
• CPC Class Codes: A61B 5/14532 for measuring glucose, e.g. by tissue impedance measurement
• CPC Class Codes: A61B 5/14546 for measuring analytes not otherwise provided for, e.g. ions, cytochromes
• CPC Class Codes: A61B 5/1473 invasive, e.g. introduced into the body by a catheter A61B5/1482 takes precedence
• CPC Class Codes: A61B 5/14865 invasive, e.g. introduced into the body by a catheter or needle or using implanted sensors
• CPC Class Codes: A61B 5/4839 combined with drug delivery
• CPC Class Codes: A61M 2205/0244 Micromachined materials, e.g. made from silicon wafers, microelectromechanical systems [MEMS] or comprising nanotechnology
• CPC Class Codes: A61N 1/05 for implantation or insertion into the body, e.g. heart electrode A61N1/06 takes precedence
• CPC Class Codes: A61N 1/3754 Feedthroughs
• CPC Class Codes: H01L 23/3107 the device being completely enclosed
• CPC Class Codes: H01L 23/5387 Flexible insulating substrates H01L23/5388 takes precedence
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/19041 being a capacitor

Abstract

The present invention provides an implantable substrate sensor comprising electronic circuitry formed within, or on, a substrate. A protective coating then covers the substrate, forming a hermetically sealed package having the circuitry under the coating. The circuitry has electrically conductive pads for communicating and/or providing power to the circuitry. Electrical pathways provide hermetic electrical connection to the conductive pads for external connection to the sealed circuitry. In a first embodiment, the pathway is a via that is made from a biocompatible material that is made hermetic by either increasing its thickness or by ion beam deposition. Alternatively, the pathways are formed from metal traces, surrounded by a biocompatible insulation material, essentially parallel to the surface of the substrate that are connected to the conductive pads by first vias and have second ends externally accessible to the sealed package to provide external electrical connection to the hermetically sealed circuitry within.

Claims

1. A hermetically sealed package suitable for implantation in living tissue, said package comprising:

a semiconductor substrate having a plurality of surfaces and having an integrated circuit formed on at least one of said surfaces, said integrated circuit having one or more electrically conductive pads for communicating and/or providing power to said integrated circuit;

one or more electrical pathways for providing electrical connection to said one or more electrically conductive pads, said pathways having first ends coupled to said one or more pads and second ends exposed for external electrical connection from said sealed package; and

an insulating material for encapsulating said integrated circuit and said semiconductor substrate surfaces except for selected portions of said seconds ends of said electrical pathways.

2. The hermetically sealed package of

claim 1

wherein said electrical pathway comprises a biocompatible hermetic via.

3. The hermetically sealed package of

claim 2

wherein said hermetic via is comprised of platinum.

4. The hermetically sealed package of

claim 3

wherein said hermetic platinum via is formed by ion beam deposition.

5. The hermetically sealed package of

claim 3

wherein said platinum via is made hermetic by having the thickness of the platinum via being at least 5 microns.

6. The hermetically sealed package of

claim 1

wherein each of said electrical pathways comprises:

a first electrically conductive via electrically coupled to one of said pads;

a metal trace having first and second ends oriented essentially parallel to the surface of the semiconductor substrate and electrically coupled at said first end to said first via, wherein said second end is at least partially externally exposed; and

wherein

said electrical pathway is surrounded by a biocompatible insulation material.

7. The hermetically sealed package of

claim 6

wherein said biocompatible insulation material is selected from the group of alumina, zirconia, or an alloy of alumina and zirconia.

8. The hermetically sealed package of

claim 6

wherein said second via is biocompatible.

9. The hermetically sealed package of

claim 8

wherein said second via is platinum.

10. The hermetically sealed package of

claim 1

wherein at least one of said electrically conductive pathways is comprised of:

a plurality of metal traces having first and second ends, including at least an innermost trace closest to said semiconductor substrate and an outermost trace furthest from said semiconductor substrate, each adjacent pair of metal traces separated by an insulating material sandwiched in-between so as to form a hermetic seal between said metal traces;

at least one interconnection via surrounded by said insulating material for interconnecting said adjacent pairs of metal traces;

at least one innermost via for interconnecting said innermost trace to at least one of said pads on said integrated circuit;

an insulating material for encapsulating said plurality of metal traces, said integrated circuit and said semiconductor substrate, wherein the second end of at least one outermost metal trace is at least partially exposed through the encapsulating insulating material for external communication; and

wherein

said combination of metal traces, sandwiched insulating material, encapsulating material and vias provides a hermetic communication path to said integrated circuit from a location external to said implantable package.

11. The hermetically sealed package of

claim 1

wherein said integrated circuit is formed on a first surface of the semiconductor substrate and said electrical pathways from said integrated circuit extend outward from said first surface.

12. The hermetically sealed package of

claim 1

1 wherein said semiconductor substrate has a second surface on a side opposite of said first surface and said second side of said substrate and is formed without electrical pathways or an integrated circuit, thereby facilitating connection of said second sides of two of said packages.

13. A method of forming an electrically conductive hermetic connection to a hermetically sealed integrated circuit, said method comprising the steps of:

forming an integrated circuit on a face of a semiconductor substrate, said integrated circuit having one or more electrically conductive pads for communicating and/or providing power to said integrated circuit;

forming one or more electrical pathways for providing electrical connection to said one or more electrically conductive pads;

said pathways having first ends coupled to said one or more pads and second ends exposed for external electrical connection from said sealed integrated circuit; and

encapsulating said semiconductor substrate and said integrated circuit except for selected portions of said second ends of said electrical pathways.

14. The method of

claim 13

wherein the step of forming one or more electrical pathways comprises the step of forming said electrical pathways from a biocompatible material.

15. The method of

claim 13

wherein the step of forming one or more electrical pathways comprises the step of forming said electrical pathways from platinum such that said electrical pathways are biocompatible.

16. The method of

claim 15

wherein the step of forming said electrical pathways from platinum comprising depositing said platinum using ion beam deposition.

17. The method of

claim 15

wherein the step of forming said electrical pathways from platinum comprising depositing a layer of platinum of at least 5 microns to cause said platinum vias to be hermetic.

18. The method of

claim 13

wherein the step of forming one or more electrical pathways comprises at least in part the steps of:

forming a first electrically conductive via electrically coupled to one of said pads;

forming a metal trace having first and second ends oriented essentially parallel to the surface of the semiconductor substrate and electrically coupled at said first end to said first via, wherein said second end of said metal trace is at least partially externally exposed; and

surrounding said electrical pathway by a biocompatible insulation material.

19. The method of

claim 18

wherein the step of surrounding said electrical pathway comprises depositing alumina to surround said electrical pathway.

20. The method of

claim 18

wherein the step of forming a second electrically coupled via comprises forming said second via from a biocompatible material.

21. The method of

claim 18

wherein the step of forming a second electrically coupled via comprises forming said second via from platinum such that said second via is biocompatible.

22. The method of

claim 13

wherein the step of forming one or more electrical pathways comprises at least in part the steps of:

forming a plurality of metal traces having first and second ends, including at least an innermost trace closest to said semiconductor substrate and an outermost trace furthest from said semiconductor substrate, each adjacent pair of metal traces separated by an insulating material sandwiched in-between so as to form a hermetic seal between said metal traces;

forming at least one interconnection via surrounded by said insulating material for interconnecting said adjacent pairs of metal traces;

forming at least one innermost via for interconnecting said innermost trace to at least one of said pads on said integrated circuit;

depositing an insulating material for encapsulating said plurality of metal traces, said integrated circuit and said semiconductor substrate;

enabling at least a portion of one said second end of an outermost metal trace to be partially externally exposed through the encapsulating insulating material for external communication; and

wherein

said combination of metal traces, sandwiched insulating material, encapsulating material and vias provides a hermetic communication path to said integrated circuit from a location external to said implantable package.

23. The method of

claim 13

additionally comprising the step of rounding at least one corner of said encapsulated integrated circuit.

24. The method of

claim 23

wherein said rounding step comprises sandblasting.

25. The method of

claim 23

wherein said rounding step comprises acid etching.