Bias network for high efficiency RF linear power amplifier

• US 20010040483A1
• Filed: 07/02/2001
• Published: 11/15/2001
• Est. Priority Date: 12/20/1999
• Status: Active Grant

• Current Assignee: Qorvo US, Inc. (Qorvo, Inc.)
• Original Assignee: RF Micro Devices Incorporated (Qorvo, Inc.)
• Inventors: Dening, David C., Jorgenson, Jon D.
• Granted Patent: US 6,404,287 B2
• Time in Patent Office: Days
• US Class Current: 330/296
• CPC Class Codes: H03F 1/302 in bipolar transistor amplifiers H03F1/303, H03F1/305, H03F1/307 take precedence
• CPC Class Codes: H03F 2200/18 the bias of the gate of a FET being controlled by a control signal

Abstract

A bias network uses resistive biasing, active biasing and current mirror biasing in combination to enhance RF power amplifier linearity and efficiency by forming a bias network that provides temperature compensation, minimizes current drain requirements for the Vbias source and reduces the level of RF linear amplifier quiescent current.

Claims

1. A linear amplifier bias network comprising:

a radio frequency bipolar junction transistor having a collector, emitter and base;

a capacitor having one end coupled to the base of the bipolar junction transistor and having an opposite end configured to receive a radio frequency signal;

a second bipolar junction transistor having a base, a collector and an emitter, wherein the collector is coupled to a dc supply voltage;

a first resistor having one end coupled to the base of the second bipolar junction transistor and having an opposite end coupled to a bias voltage source; and

a second resistor having a first end coupled to the emitter and having a second end coupled to the base of the radio frequency bipolar junction transistor, the second resistor having a resistance value rendering the linear amplifier bias network capable of minimizing gain expansion associated with the radio-frequency bipolar junction transistor.

2. The linear amplifier bias network according to

claim 1

further comprising a third resistor having one end coupled to the bias voltage source and having an opposite end coupled to the second end of the second resistor, wherein the second and third resistors are capable of adjusting a bias impedance associated with the bias network such that the bias network can achieve a desired temperature compensation characteristic.

3. The linear amplifier bias network according to

claim 2

further comprising:

a ground node;

a third bipolar junction transistor having a base, collector and emitter, wherein the emitter of the third bipolar junction transistor is coupled to the ground node;

a fourth resistor having one end coupled to the base of the third bipolar junction transistor and having an opposite end coupled to the second end of the second resistor; and

a fifth resistor having one end coupled to the collector of the third bipolar junction transistor and having an opposite end coupled to the second end of the second resistor;

wherein a combination of resistance values for the first, second, third, fourth and fifth resistors are capable of adjusting a bias impedance associated with the bias network such that the bias network can achieve a desired temperature compensation characteristic and further such that the bias network can achieve a desired level of quiescent current and minimize gain expansion associated with the radio frequency bipolar junction transistor.

4. The linear amplifier bias network according to

claim 3

wherein the bias voltage source comprises a resistor/diode network coupled to a supply voltage to generate a desired supply reference voltage.

5. The linear amplifier bias network according to

claim 3

wherein the bias voltage source comprises:

a diode network; and

a resistor having a first end coupled to a supply voltage and having an opposite end coupled to the diode network such that a predetermined voltage drop is achieved across the diode network relative to the ground node to produce a desired bias voltage for the linear amplifier bias network.

6. The linear amplifier bias network according to

claim 5

wherein the diode network comprises a plurality of diodes and a series resistor.

7. The linear amplifier bias network according to

claim 3

wherein the bias voltage source comprises:

a transistor network configured as a diode network; and

a resistor having a first end coupled to a supply voltage and having an opposite end coupled to the transistor network such that a predetermined voltage drop is achieved across the transistor network relative to the ground node to produce a desired supply reference voltage for the linear amplifier bias network.

8. The linear amplifier bias network according to

claim 7

wherein the transistor network comprises a plurality of bipolar junction transistors and a series resistor.

9. The linear amplifier bias network according to

claim 8

further comprising an inductor having a first end coupled to the ground node and further having an opposite end coupled to the emitter of the third bipolar junction transistor such that the emitter of the third bipolar junction transistor is coupled to the ground node solely through the inductor.

10. The linear amplifier bias network according to

claim 9

wherein the emitter of the third bipolar junction transistor is further coupled to the transistor network such that a portion of he transistor network is coupled to the ground node solely through the inductor.

11. The linear amplifier bias network according to

claim 9

wherein any single resistor selected from the group consisting of the first, second, third, fourth and fifth resistors is configured to have zero resistance.

12. The linear amplifier bias network according to

claim 2

further comprising:

a ground node; and

a third bipolar junction transistor having a base, collector and emitter, wherein the emitter of the third bipolar junction transistor is coupled to the ground node and wherein the base and collector of the third bipolar junction transistor are coupled to the second end of the second resistor.

13. The linear amplifier bias network according to

claim 12

wherein the bias voltage source comprises a resistor/diode network coupled to a supply voltage to generate a desired supply reference voltage.

14. The linear amplifier bias network according to

claim 12

wherein the bias voltage source comprises:

a diode network; and

a resistor having a first end coupled to a supply voltage and having an opposite end coupled to the diode network such that a predetermined voltage drop is achieved across the diode network relative to the ground node to produce a desired bias voltage for the linear amplifier bias network.

15. The linear amplifier bias network according to

claim 14

wherein the diode network comprises a plurality of diodes and a series resistor.

16. The linear amplifier bias network according to

claim 11

wherein the bias voltage source comprises:

a transistor network configured as a diode network; and

a resistor having a first end coupled to a supply voltage and having an opposite end coupled to the transistor network such that a predetermined voltage drop is achieved across the transistor network relative to the ground node to produce a desired supply reference voltage for the linear amplifier bias network.

17. The linear amplifier bias network according to

claim 16

wherein the transistor network comprises a plurality of bipolar junction transistors and a series resistor.

18. The linear amplifier bias network according to

claim 17

further comprising an inductor having a first end coupled to the ground node and further having an opposite end coupled to the emitter of the third bipolar junction transistor such that the emitter of the third bipolar junction transistor is coupled to the ground node solely through the inductor.

19. The linear amplifier bias network according to

claim 18

wherein any single resistor selected from the group consisting of the first, second and third resistors is configured to have zero resistance.

20. The linear amplifier bias network according to

claim 18

wherein the emitter of the third bipolar junction transistor is further coupled to the transistor network such that a portion of the transistor network is coupled to the ground node solely through the inductor.

21. The linear amplifier bias network according to

claim 20

wherein any single resistor selected from the group consisting of the first, second and third resistors is configured to have zero resistance.

22. The linear amplifier bias network according to

claim 2

further comprising:

a ground node;

a third bipolar junction transistor having a base, collector and emitter, wherein the emitter of the third bipolar junction transistor is coupled to the ground node and wherein the collector of the third bipolar junction transistor is coupled to the second end of the second resistor; and

a fourth resistor having one end coupled to the base of the third bipolar junction transistor and having an opposite end coupled to the second end of the second resistor, wherein a combination of resistance values for the first, second, third and fourth resistors are capable of adjusting a bias impedance associated with the bias network such that the bias network can achieve a desired temperature compensation characteristic and further such that the bias network can achieve a desired level of quiescent current and minimize gain expansion associated with the radio frequency bipolar junction transistor.

23. The linear amplifier bias network according to

claim 22

wherein the bias voltage source comprises a resistor/diode network coupled to a supply voltage to generate a desired supply reference voltage.

24. The linear amplifier bias network according to

claim 22

wherein the bias voltage source comprises:

a diode network; and

a resistor having a first end coupled to a supply voltage and having an opposite end coupled to the diode network such that a predetermined voltage drop is achieved across the diode network relative to the ground node to produce a desired bias voltage for the linear amplifier bias network.

25. The linear amplifier bias network according to

claim 24

wherein the diode network comprises a plurality of diodes and a series resistor.

26. The linear amplifier bias network according to

claim 22

wherein the bias voltage source comprises:

a transistor network configured as a diode network; and

a resistor having a first end coupled to a supply voltage and having an opposite end coupled to the transistor network such that a predetermined voltage drop is achieved across the transistor network relative to the ground node to produce a desired supply reference voltage for the linear amplifier bias network.

27. The linear amplifier bias network according to

claim 26

wherein the transistor network comprises a plurality of bipolar junction transistors and a series resistor.

28. The linear amplifier bias network according to

claim 27

further comprising an inductor having a first end coupled to the ground node and further having an opposite end coupled to the emitter of the third bipolar junction transistor such that the emitter of the third bipolar junction transistor is coupled to the ground node solely through the inductor.

29. The linear amplifier bias network according to

claim 28

wherein any single resistor selected from the group consisting of the first, second, third and fourth resistors is configured to have zero resistance.

30. The linear amplifier bias network according to

claim 28

wherein the emitter of the third bipolar junction transistor is further coupled to the transistor network such that a portion of the transistor network is coupled to the ground node solely through the inductor.

31. The linear amplifier bias network according to

claim 30

wherein any single resistor selected from the group consisting of the first, second, third and fourth resistors is configured to have zero resistance.

32. The linear amplifier bias network according to

claim 2

further comprising:

a ground node;

a third bipolar junction transistor having a base, collector and emitter, wherein the emitter of the third bipolar junction transistor is coupled to the ground node and wherein the base of the third bipolar junction transistor is coupled to the second end of the second resistor; and

a fourth resistor having one end coupled to the collector of the third bipolar junction transistor and having an opposite end coupled to the second end of the second resistor, wherein a combination of resistance values for the first, second, third and fourth resistors are capable of adjusting a bias impedance associated with the bias network such that the bias network can achieve a desired temperature compensation characteristic and further such that the bias network can achieve a desired level of quiescent current and minimize gain expansion associated with the radio frequency bipolar junction transistor.

33. The linear amplifier bias network according to

claim 32

wherein the bias voltage source comprises a resistor/diode network coupled to a supply voltage and configured to generate a desired supply reference voltage.

34. The linear amplifier bias network according to

claim 32

wherein the bias voltage source comprises:

a diode network; and

a resistor having a first end coupled to a supply voltage and having an opposite end coupled to the diode network such that a predetermined voltage drop is achieved across the diode network relative to the ground node to produce a desired bias voltage for the linear amplifier bias network.

35. The linear amplifier bias network according to

claim 34

wherein the diode network comprises a plurality of diodes and a series resistor.

36. The linear amplifier bias network according to

claim 32

wherein the bias voltage source comprises:

a transistor network configured as a diode network; and

a resistor having a first end coupled to a supply voltage and having an opposite end coupled to the transistor network such that a predetermined voltage drop is achieved across the transistor network relative to the ground node to produce a desired supply reference voltage for the linear amplifier bias network.

37. The linear amplifier bias network according to

claim 36

wherein the transistor network comprises a plurality of bipolar junction transistors and a series resistor.

38. The linear amplifier bias network according to

claim 37

further comprising an inductor having a first end coupled to the ground node and further having an opposite end coupled to the emitter of the third bipolar junction transistor such that the emitter of the third bipolar junction transistor is coupled to the ground node solely through the inductor.

39. The linear amplifier bias network according to

claim 38

wherein any single resistor selected from the group consisting of the first, second, third and fourth resistors is configured to have zero resistance.

40. The linear amplifier bias network according to

claim 38

wherein the emitter of the third bipolar junction transistor is further coupled to the transistor network such that a portion of the transistor network is coupled to the ground node solely through the inductor.

41. The linear amplifier bias network according to

claim 40

wherein any single resistor selected from the group consisting of the first, second, third and fourth resistors is configured to have zero resistance.

42. A linear amplifier bias network comprising:

a radio frequency bipolar junction transistor having a base, collector and emitter;

a capacitor having one end coupled to the base of the radio frequency bipolar junction transistor and having an opposite end configured to receive a radio frequency input signal;

a second bipolar junction transistor having a base, collector and emitter, wherein the collector of the second bipolar junction transistor is coupled to a dc supply voltage;

a first resistor having one end coupled to the base of the second bipolar junction transistor and an opposite end coupled to a bias voltage source;

a second resistor having one end coupled to the emitter of the second bipolar junction transistor and having a second end configured to supply a bias current; and

a third resistor having one end coupled to the bias voltage source and an opposite end coupled to the second end of the second resistor, wherein a combination of resistance values for the first, second and third resistors render the linear amplifier bias network capable of minimizing gain expansion associated with the radio frequency bipolar junction transistor and further wherein a combination of resistance values for the first, second and third resistors are capable of adjusting a bias impedance associated with the bias network such that the bias network can achieve a desired temperature compensation characteristic and further such that the bias network can achieve a desired level of quiescent current associated with the radio frequency bipolar junction transistor.

43. The linear amplifier bias network according to

claim 42

further comprising:

a ground node;

a third bipolar junction transistor having a base, collector and emitter, wherein the emitter of the third bipolar junction transistor is coupled to the ground node;

a fourth resistor having one end coupled to the base of the third bipolar junction transistor and having an opposite end coupled to the second end of the second resistor; and

a fifth resistor having one end coupled to the collector of the third bipolar junction transistor and having an opposite end coupled to the second end of the second resistor;

wherein a combination of resistance values for the first, second, third, fourth and fifth resistors are capable of adjusting a bias impedance associated with the bias network such that the bias network can achieve a desired temperature compensation characteristic and further such that the bias network can achieve a desired level of quiescent current associated with the radio frequency bipolar junction transistor.

44. The linear amplifier bias network according to

claim 43

wherein the bias voltage source comprises a resistor/diode network coupled to a supply voltage and configured to generate a desired reference supply voltage.

45. The linear amplifier bias network according to

claim 43

wherein the bias voltage source comprises:

a diode network; and

a resistor having a first end coupled to a supply voltage and having an opposite end coupled to the diode network such that a predetermined voltage drop is achieved across the diode network relative to the ground node to produce a desired bias voltage for the linear amplifier bias network.

46. The linear amplifier bias network according to

claim 45

wherein the diode network comprises a plurality of diodes and a series resistor.

47. The linear amplifier bias network according to

claim 43

wherein the bias voltage source comprises:

a transistor network configured as a diode network; and

a resistor having a first end coupled to a supply voltage and having an opposite end coupled to the transistor network such that a predetermined voltage drop is achieved across the transistor network relative to the ground node to produce a desired supply reference voltage for the linear amplifier bias network.

48. The linear amplifier bias network according to

claim 47

wherein the transistor network comprises a plurality of bipolar junction transistors and a series resistor.

49. The linear amplifier bias network according to

claim 48

further comprising an inductor having a first end coupled to the ground node and further having an opposite end coupled to the emitter of the third bipolar junction transistor such that the emitter of the third bipolar junction transistor is coupled to the ground node solely through the inductor.

50. The linear amplifier bias network according to

claim 49

wherein any single resistor selected from the group consisting of the first, second, third, fourth and fifth resistors is configured to have zero resistance.

51. The linear amplifier bias network according to

claim 49

wherein the emitter of the third bipolar junction transistor is further coupled to the transistor network such that a portion of the transistor network is coupled to the ground node solely through the inductor.

52. The linear amplifier bias network according to

claim 51

wherein any single resistor selected from the group consisting of the first, second, third, fourth and fifth resistors is configured to have zero resistance.

53. A linear amplifier bias network comprising:

a radio frequency bipolar junction transistor having a base, collector and emitter;

a capacitor having one end coupled to the base of the bipolar junction transistor and having an opposite end configured to receive a radio frequency input signal;

a ground node;

a second bipolar junction transistor having a base, collector and emitter, wherein the emitter of the second bipolar junction transistor is coupled to the ground node;

a first resistor having one end coupled to a bias voltage source and further having a second end coupled to the base of the radio frequency bipolar junction transistor;

a second resistor having one end coupled to the base of the second bipolar junction transistor and having an opposite end coupled to the second end of the first resistor; and

a third resistor having one end coupled to the collector of the second bipolar junction transistor and having an opposite end coupled to the second end of the first resistor;

wherein a combination of resistance values for the first, second and third resistors are capable of adjusting a bias impedance associated with the bias network such that the bias network can achieve a desired temperature compensation characteristic and further such that the bias network can achieve a desired level of quiescent current and minimize gain expansion associated with the radio frequency bipolar junction transistor.

54. The linear amplifier bias network according to

claim 53

further comprising an inductor having a first end coupled to the ground node and further having an opposite end coupled to the emitter of the second bipolar junction transistor such that the emitter of the second bipolar junction transistor is coupled to the ground node solely through the inductor.

55. The linear amplifier bias network according to

claim 54

further comprising:

a third bipolar junction transistor having a base, collector and emitter, wherein the collector of the third bipolar junction transistor is coupled to a de supply voltage;

a fourth resistor having a first end coupled to the emitter of the third bipolar junction transistor and having a second end coupled to the second end of the first resistor; and

a fifth resistor having a first end coupled to the base of the third bipolar junction transistor and having an opposite end coupled to the bias voltage supply;

wherein a combination of resistance values for the first, second, third, fourth and fifth resistors are capable of adjusting a bias impedance associated with the bias network such that the bias network can achieve a desired temperature compensation characteristic and further such that the bias network can achieve a desired level of quiescent current and minimize gain expansion associated with the radio frequency bipolar junction transistor.

56. The linear amplifier bias network according to

claim 55

wherein any single resistor selected from the group consisting of the first, second, third, fourth and fifth resistors is configured to have zero resistance.

57. The linear amplifier bias network according to

claim 54

wherein the bias voltage source comprises a resistor/diode network coupled to a supply voltage and configured to generate a desired reference supply voltage.

58. The linear amplifier bias network according to

claim 54

wherein the bias voltage source comprises:

a diode network having a first node and a second node; and

a resistor having a first end coupled to a supply voltage and having an opposite end coupled to the diode network first node such that a predetermined voltage drop is achieved across the diode network relative to the ground node to produce a desired bias voltage for the linear amplifier bias network.

59. The linear amplifier bias network according to

claim 58

wherein the diode network includes at least one series resistor.

60. The linear amplifier bias network according to

claim 59

further comprising an inductor having a first end coupled to the ground node and further having an opposite end coupled to the diode network such that a portion of the diode network is coupled to the ground node solely through the inductor.

61. The linear amplifier bias network according to

claim 60

wherein any single resistor selected from the group consisting of the first, second and third resistors is configured to have zero resistance.

62. The linear amplifier bias network according to

claim 54

wherein the bias voltage source comprises:

a transistor network configured as a diode network; and

a resistor having a first end coupled to a supply voltage and having an opposite end coupled to the transistor network such that a predetermined voltage drop is achieved across the transistor network relative to the ground node to produce a desired supply reference voltage for the linear amplifier bias network.

63. The linear amplifier bias network according to

claim 62

wherein the transistor network includes a series resistor.

64. The linear amplifier bias network according to

claim 63

further comprising an inductor having a first end coupled to the ground node and further having an opposite end coupled to the transistor network such that a portion of the transistor network is coupled to the ground node solely through the inductor.

65. The linear amplifier bias network according to

claim 64

wherein any single resistor selected from the group consisting of the first, second and third resistors is configured to have zero resistance.

66. A linear amplifier bias network comprising:

a radio frequency bipolar junction transistor having a base, collector and emitter;

a capacitor having one end coupled to the base of the radio frequency bipolar junction transistor and having an opposite end configured to receive a radio frequency input signal;

a ground node;

a second bipolar junction transistor having a base, collector and emitter, wherein the base of the second bipolar junction transistor is coupled to the collector of the second bipolar junction transistor and further wherein the base of the second bipolar junction transistor is coupled to the base of the radio frequency bipolar junction transistor;

a first resistor having one end coupled to a bias voltage source and having a second end coupled to the collector of the second bipolar junction transistor; and

a first inductor having one end coupled to the emitter of the second bipolar junction transistor and having an opposite end coupled to the ground node;

wherein a combination of impedance values for the first resistor and the first inductor is capable of adjusting a bias impedance associated with the bias network such that the bias network can achieve a desired temperature compensation characteristic and further such that the bias network can achieve a desired level of quiescent current associated with the radio frequency bipolar junction transistor.

67. The linear amplifier bias network according to

claim 66

further comprising:

a third bipolar junction transistor having a base, collector and emitter, wherein the collector of the third bipolar junction transistor is coupled to a dc supply voltage;

a second resistor having one end coupled to the base of the third bipolar junction transistor and having an opposite end coupled to the bias voltage supply; and

a third resistor having one end coupled to the emitter of the third bipolar junction transistor and having an opposite end coupled to the collector of the second bipolar junction transistor, wherein a combination of impedance values for the inductor and resistance values for the first, second and third resistors are capable of adjusting a bias impedance associated with the bias network such that the bias network can achieve a desired temperature compensation characteristic and further such that the bias network can achieve a desired level of quiescent current associated with the radio frequency bipolar junction transistor.

68. The linear amplifier bias network according to

claim 67

wherein any single resistor selected from the group consisting of the first, second and third resistors is configured to have zero resistance.

69. The linear amplifier bias network according to

claim 66

wherein the bias voltage source comprises a resistor/diode network coupled to a supply voltage and configured to generate a desired reference supply voltage.

70. The linear amplifier bias network according to

claim 66

wherein the bias voltage source comprises:

a diode network; and

a resistor having a first end coupled to a supply voltage and having an opposite end coupled to the diode network such that a predetermined voltage drop is achieved across the diode network relative to the ground node to produce a desired bias voltage for the linear amplifier bias network.

71. The linear amplifier bias network according to

claim 70

wherein the diode network includes a series resistor.

72. The linear amplifier bias network according to

claim 71

further comprising a second inductor having a first end coupled to the ground node and further having an opposite end coupled to the diode network such that a portion of the diode network is coupled to the ground node solely through the second inductor.

73. The linear amplifier bias network according to

claim 71

wherein the diode network is coupled to the first inductor such that a portion of the diode network is coupled to the ground node solely through the first inductor.

74. The linear amplifier bias network according to

claim 66

wherein the bias voltage source comprises:

a transistor network configured as a diode network; and

a resistor having a first end coupled to a supply voltage and having an opposite end coupled to the transistor network such that a predetermined voltage drop is achieved across the transistor network relative to the ground node to produce a desired supply reference voltage for the linear amplifier bias network.

75. The linear amplifier bias network according to

claim 74

wherein the transistor network comprises a plurality of bipolar junction transistors and a series resistor.

76. The linear amplifier bias network according to

claim 75

further comprising a second inductor having a first end coupled to the ground node and further having an opposite end coupled to the transistor network such that a portion of the transistor network is coupled to the ground node solely through the second inductor.

77. The linear amplifier bias network according to

claim 75

wherein the transistor network is coupled to the first inductor such that a portion of the transistor network is coupled to the ground node solely through the first inductor.

78. A linear amplifier bias network comprising:

a radio frequency bipolar junction transistor having a base, collector and emitter;

a capacitor having one end coupled to the base of the radio frequency bipolar junction transistor and having an opposite end configured to receive a radio frequency input signal;

a buffered passive bias network having a first bipolar junction transistor and further having an emitter resistor associated with the first bipolar junction transistor; and

a current mirror bias network coupled to the buffered passive bias network, the current mirror bias network having a second bipolar junction transistor and further having a collector resistor and a base resistor associated with the second bipolar junction transistor;

wherein a combination of resistance values for the emitter, base and collector resistors are capable of adjusting a bias impedance associated with the bias network such that the bias network can achieve a desired temperature compensation characteristic and further such that the bias network can achieve a desired level of quiescent current and minimize gain expansion associated with the radio frequency bipolar junction transistor.

79. The linear amplifier bias network according to

claim 78

further comprising an inductor having a first end coupled to a ground node and further having an opposite end coupled to the emitter of the second bipolar junction transistor such that the emitter of the second bipolar junction transistor is coupled to the ground node solely through the inductor.

80. The linear amplifier bias network according to

claim 79

wherein any single resistor selected from the group consisting of the emitter resistor, the collector resistor and the base resistor is configured to have zero resistance.

81. The linear amplifier bias network according to

claim 78

further comprising:

a supply voltage node;

a ground node;

a diode network; and

a resistor having a first end coupled to the supply voltage node and having an opposite end coupled to the diode network such that a predetermined voltage drop is achieved across the diode network relative to the ground node to produce a desired bias voltage for the linear amplifier bias network.

82. The linear amplifier bias network according to

claim 81

wherein the diode network includes a plurality of diodes and a series resistor.

83. The linear amplifier bias network according to

claim 82

further comprising an inductor having a first end coupled to the ground node and further having an opposite end coupled to the diode network such that a portion of the diode network is coupled to the ground node solely through the inductor.

84. The linear amplifier bias network according to

claim 83

wherein any single resistor selected from the group consisting of the emitter resistor, the collector resistor and the base resistor is configured to have zero resistance.

85. The linear amplifier bias network according to

claim 78

further comprising:

a supply voltage node;

a ground node;

a transistor network configured as a diode network; and

a resistor having a first end coupled to the supply voltage node and having an opposite end coupled to the transistor network such that a predetermined voltage drop is achieved across the transistor network relative to the ground node to produce a desired bias voltage for the linear amplifier bias network.

86. The linear amplifier bias network according to

claim 85

wherein the transistor network includes a plurality of bipolar junction transistors and a series resistor.

87. The linear amplifier bias network according to

claim 86

further comprising an inductor having a first end coupled to the ground node and further having an opposite end coupled to the transistor network such that a portion of the transistor network is coupled to the ground node solely through the inductor.

88. The linear amplifier bias network according to

claim 87

wherein any single resistor selected from the group consisting of the emitter resistor, the collector resistor and the base resistor is configured to have zero resistance.

89. A linear amplifier bias network comprising:

a radio frequency bipolar junction transistor having a base, collector and emitter;

a capacitor having one end coupled to the base of the radio frequency bipolar junction transistor and having an opposite end configured to receive a radio frequency input signal;

a buffered passive bias network having a first bipolar junction transistor and further having at least one emitter resistor associated with the first bipolar junction transistor; and

a current mirror bias network coupled to the buffered passive bias network, the current mirror bias network having a second bipolar junction transistor and further having at least one emitter inductor associated with the second bipolar junction transistor;

wherein a combination of impedance values for the at least one emitter resistor and at least one emitter inductor are capable of adjusting a bias impedance associated with the bias network such that the bias network can achieve a desired temperature compensation characteristic and further such that the bias network can achieve a desired level of quiescent current associated with the radio frequency bipolar junction transistor.

90. A linear amplifier bias network comprising:

a radio frequency bipolar junction transistor having a base, collector and emitter;

a capacitor having a first end coupled to the base of the radio frequency bipolar junction transistor and having an opposite end configured to receive a radio frequency input signal;

an active bias network having a first bipolar junction transistor and a base resistor; and

means for establishing an impedance in the emitter leg of the first bipolar junction transistor to achieve a desired level of quiescent bias current associated with the radio frequency bipolar junction transistor, wherein the means for establishing the impedance is independent of the base resistor.

91. The linear amplifier bias network according to

claim 90

further comprising first means for establishing an impedance for the linear amplifier bias network to achieve a desired first temperature compensation characteristic wherein the first means for establishing an impedance for the linear amplifier bias network is independent of the means for establishing an impedance in the emitter leg of the first bipolar junction transistor and is further independent of the base resistor.

92. The linear amplifier bias network according to

claim 91

further comprising second means for establishing an impedance for the linear amplifier bias network to achieve a desired second temperature compensation characteristic wherein the second means for establishing an impedance for the linear amplifier bias network is independent of the first means and the means for establishing an impedance in the emitter leg of the first bipolar junction transistor and is further independent of the base resistor.

93. The linear amplifier bias network according to

claim 92

wherein the second means comprises a bipolar junction transistor having a base, a collector and an emitter, and further comprising an inductor having a first end coupled to the emitter of the bipolar junction transistor and having an opposite end coupled to a ground node.

94. A method of producing a desired temperature compensation characteristic associated with a linear amplifier bias network comprising the steps of:

providing a radio frequency bipolar junction transistor having a base, collector and emitter;

providing a capacitor having a first end coupled to the base of the radio frequency bipolar junction transistor and further having an opposite end configured to receive a radio frequency input signal;

providing an active bias network having a first bipolar junction transistor and a base resistor associated therewith;

providing an emitter resistor associated with the first bipolar junction transistor; and

adjusting the resistance of the emitter resistor to achieve a desired temperature compensation characteristic for the radio frequency bipolar junction transistor.

95. The method of

claim 94

further comprising the step of modifying the active bias network with a second resistor to produce a buffered passive bias network.

96. The method of

claim 95

further comprising the step of adjusting the resistance of the second resistor and the emitter resistor to achieve a desired impedance for the buffered passive bias network and further to achieve a desired level of quiescent bias current for the radio frequency bipolar junction transistor.

97. The method of

claim 96

further comprising the step of coupling a current mirror bias network to the buffered passive bias network.

98. The method of

claim 97

further comprising the step of adjusting the impedance of the current mirror bias network and the buffered passive bias network in combination to achieve a desired temperature compensation characteristic for the linear amplifier bias network and further to achieve a desired quiescent bias current for the radio frequency bipolar junction transistor.