BUFFERING SYSTEM BUS FOR EXTERNAL-MEMORY ACCESS

• US 20010052060A1
• Filed: 07/12/1999
• Published: 12/13/2001
• Est. Priority Date: 07/12/1999
• Status: Active Grant

• Current Assignee: Invensas Corporation
• Original Assignee: Koninklijke Philips Electronics N.V. (Koninklijke Philips N.V.)
• Inventors: BAO, LIEWEI
• Granted Patent: US 6,708,257 B2
• Time in Patent Office: Days
• US Class Current: 711/167
• CPC Class Codes: G06F 13/1673 using buffers

Abstract

A computer system includes a processor, a cache, a system bus, a memory-control subsystem, an external memory bus, RAM memory, and flash memory. All but the last three are fabricated on a single ASIC. The memory control subsystem includes a RAM controller, a flash-memory controller, and a memory interface between the controllers and the memories. In addition, the memory-control subsystem includes a system-bus FIFO write buffer. During an external-memory access, the request information is transferred from the system bus to the system-bus buffer instead of directly to the memory interface. The system-bus buffer stores address data, content data (in the case of a write request), and control data. In turn, the control data is forwarded to the appropriate controller and the address data and the content data are forwarded to external memory bus. Note that only one system-bus write buffer is required despite the plural memory controllers. While the processor write buffer frees the processor for other tasks while a write operation is being completed, the system-bus write buffer frees the system bus for other tasks while a write operation is being completed. The system-bus buffer thus allows other operations to utilize the system bus during an external-memory access.

Claims

1. A computer system comprising:

memory;

a processor that issues data-transfer requests directed to said memory; and

a transfer path for conveying data-transfer requests including write requests between said processor and said memory, said transfer path including

a system bus, and

a system-bus buffer disposed between said system bus and said memory, said system-bus buffer being coupled to said system bus for storing said data-transfer requests, said system-bus buffer being coupled to said memory for providing said data-transfer requests thereto.

2. A system as recited in

claim 1

wherein said transfer path further includes a processor write buffer disposed between said processor and said system bus.

3. A system as recited in

claim 1

further comprising a first memory controller and a second memory controller, said memory including a first memory and a second memory, said first memory being controlled by said first memory controller, said second memory being controlled by said second memory controller, said first and second memory controllers being coupled to said system-bus buffer for receiving control data associated with said data-transfer requests therefrom.

4. A system as recited in

claim 1

wherein said data-transfer requests include read requests, said system-bus buffer storing at least some of said read requests.

5. A system as recited in

claim 4

wherein at least some of said read requests are fulfilled from said memory without being stored by said system-bus buffer.

6. A method for executing a write request, said method comprising the steps of:

issuing said write request from a processor;

transferring said write request to a system-bus buffer via a system bus, and

transferring said write request from said system-bus buffer to a main memory.

7. A method as recited in

claim 6

further comprising the step of:

after assigning said write request and before transferring said write request to said system-bus buffer via said system bus, transferring said write request to a processor write buffer.

8. A method as recited in

claim 6

wherein said step of transferring said write request from said system-bus buffer to a main memory selecting one of plural memory controllers coupled to said main memory and said system bus as a function of device-select data associated with said write request.