Integrated verification and manufacturability tool

• US 20010052107A1
• Filed: 12/22/2000
• Published: 12/13/2001
• Est. Priority Date: 06/13/2000
• Status: Active Grant

• Current Assignee: Siemens Industry Software Limited (Siemens AG)
• Original Assignee: Mentor Graphics Corporation (Siemens AG)
• Inventors: Cobb, Nicolas B., Sahouria, Emile, Grodd, Laurence W., You, Siqiong, Anderson, Leigh C.
• Granted Patent: US 6,415,421 B2
• Time in Patent Office: Days
• US Class Current: 716/52
• CPC Class Codes: G03F 1/26 Phase shift masks [PSM]; PSM blanks; Preparation thereof
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

An integrated verification and manufacturability tool provides more efficient verification of integrated device designs than verification using several different verification tools. The integrated verification and manufacturability includes a hierarchical database to store shared design data accessed by multiple verification tool components (e.g., layout versus schematic, design rule check, optical process correction, phase shift mask assignment and machine language conversion). The hierarchical database includes representations of one or more additional, or intermediate layer structures that are created and used by the verification tool components for operations performed on the design being verified. Use of a single hierarchical database having shared data for access and use by multiple verification components streamlines the verification process, which provides an improved verification tool.

Claims

1. An integrated verification and manufacturability tool comprising:

a hierarchical database to represent at least a portion of an integrated device layout in a hierarchical manner;

a checking component to operate on the integrated device design by accessing said database; and

an optical process correction (OPC) component to operate on the integrated device layout by accessing said database.

2. The integrated verification and manufacturability tool of

claim 1

, wherein the checking component comprises a layout versus schematic (LVS) component.

3. The integrated verification and manufacturability tool of

claim 1

, wherein the checking component comprises a design rule checking (DRC) component.

4. The integrated verification and manufacturability tool of

claim 1

, further comprising a phase shift mask (PSM) component.

5. The integrated verification and manufacturability tool of

claim 1

, further comprising an optical rule checking (ORC) component.

6. The integrated verification and manufacturability tool of

claim 1

, wherein the OPC component and the checking component operate on sets of edges that represent a portion of the integrated device layout.

7. The integrated verification and manufacturability tool of

claim 1

, wherein the integrated device layout is an integrated circuit (IC) layout.

8. The integrated verification and manufacturability tool of

claim 1

, wherein the hierarchical database includes one or more intermediate layers.

9. The integrated verification and manufacturability tool of

claim 8

, wherein a number of intermediate layers to be included in the hierarchical database is determined based, at least in part, on operations to be performed on the integrated device layout.

10. A method comprising:

importing an integrated device layout into a hierarchical database to create shared data;

performing layout verification operations on the shared data; and

performing optical process correction (OPC) operations on the shared data.

11. The method of

claim 10

, wherein performing layout verification operations comprises performing layout versus schematic (LVS) operations on the shared data.

12. The method of

claim 10

, wherein performing layout verification operations comprises performing design rule checking (DRC) operations on the shared data.

13. The method of

claim 10

, wherein performing layout verification operations comprises performing design rule checking (DRC) operations on simulated silicon edges within the shared data.

14. The method of

claim 10

, further comprising performing phase shift mask (PSM) operations on the shared data.

15. The method of

claim 10

, further comprising performing optical rule checking (ORC) operations on the shared data.

16. The method of

claim 10

, wherein importing an integrated device layout into the hierarchical database comprises analyzing an original integrated device layout for redundant patterns and replacing one or more of the redundant patterns with cells that include the redundant patterns.

17. The method of

claim 10

, wherein importing an integrated device layout into the hierarchical database comprises converting one or more portions of the layout comprising a single layer to one or more portions of the layout comprising multi-level hierarchical layouts.

18. The method of

claim 10

, wherein the layout verification operations and the optical process correction (OPC) operations are performed on a set of edges that represent portions of the integrated device layout within the shared data.

19. The method of

claim 10

, wherein the integrated device layout comprises an integrated circuit (IC) layout.

20. A machine-readable medium having stored thereon sequences of instructions that, when executed, cause one or more electronic systems to:

import an integrated device layout to a hierarchical database to create shared data;

perform layout verification operations on the integrated device design on the shared data; and

perform optical process correction (OPC) operations on the shared data.

21. The machine-readable medium of

claim 20

, wherein the sequences of instructions that cause the one or more electronic systems to perform layout operations comprises sequences of instructions that, when executed, cause the one or more electronic systems to perform layout versus schematic (LVS) operations on the shared data.

22. The machine-readable medium of

claim 20

, wherein the sequences of instructions that cause the one or more electronic systems to perform layout operations comprises sequences of instructions that, when executed, cause the one or more electronic systems to perform design rule checking (DRC) operations on the shared data.

23. The machine-readable medium of

claim 20

, further comprising sequences of instructions that, when executed, cause the one or more electronic systems to perform phase shift mask (PSM) operations on the shared data.

24. The machine-readable medium of

claim 20

, further comprising sequences of instructions that, when executed, cause the one or more electronic systems to perform optical rule checking (ORC) operations on the shared data.

25. The machine-readable medium of

claim 20

, further comprising sequences of instructions that, when executed, cause the one or more electronic systems to perform optical rule checking (ORC) operations on simulated silicon edges within the shared data.

26. The machine-readable medium of

claim 20

, wherein the sequences of instructions that cause the one or more electronic systems to import an integrated device layout into the hierarchical database comprises sequences of instructions that, when executed, cause the one or more electronic systems to analyze an original integrated device layout for redundant patterns and replacing one or more of the redundant patterns with cells that include redundant patterns.

27. The machine-readable medium of

claim 20

, wherein the sequences of instructions that cause the one or more electronic systems to import an integrated device layout to the hierarchical database comprises sequences of instructions that, when executed, cause the one or more electronic systems to convert one or more portions of the layout comprising a single layer to one or more portions of the layout comprising multi-level hierarchical layouts.

28. The machine-readable medium of

claim 20

, wherein the layout verification operations and the optical process correction (OPC) operations are performed on a set of edges the represent portions of the integrated device layout within the shared data.

29. The machine-readable medium of

claim 20

, wherein the integrated device layout comprises an integrated circuit (IC) layout.

30. A computer data signal embodied in a data communications medium shared among a plurality of network devices comprising sequences of instructions that, when executed, cause one or more electronic systems to:

import an integrated device layout into a hierarchical database;

perform layout verification operations on the integrated device design; and

perform optical process correction (OPC) operations on the integrated device design.

31. The electronic data signal of

claim 30

, wherein the sequences of instructions that cause the one or more electronic systems to perform layout operations comprises sequences of instructions that, when executed, cause the one or more electronic systems to perform layout versus schematic (LVS) operations on the integrated device layout.

32. The electronic data signal of

claim 30

, wherein the sequences of instructions that cause the one or more electronic systems to perform layout operations comprises sequences of instructions that, when executed, cause the one or more electronic systems to perform design rule checking (DRC) operations on the integrated device layout.

33. The electronic data signal of

claim 30

, further comprising sequences of instructions that, when executed, cause the one or more electronic systems to perform phase shift mask (PSM) operations on the integrated device layout.

34. The electronic data signal of

claim 30

, further comprising sequences of instructions that, when executed, cause the one or more electronic systems to perform optical rule checking (ORC) operations on the integrated device layout.

35. The electronic data signal of

claim 30

, further comprising sequences of instructions that, when executed, cause the one or more electronic systems to perform optical rule checking (ORC) operations on simulated silicon edges.

36. The electronic data signal of

claim 30

, wherein the sequences of instructions that cause the one or more electronic systems to import an integrated device layout to the hierarchical database comprises sequences of instructions that, when executed, cause the one or more electronic systems to analyze an original integrated device design for redundant patterns and replace one or more of the redundant patterns with cells that include the redundant patterns.

37. The electronic data signal of

claim 30

, wherein the sequences of instructions that cause the one or more electronic systems to import an integrated device layout to the hierarchical database comprises sequences of instructions that, when executed, cause the one or more electronic systems to convert one or more portions of the layout comprising a single layer to one or more portions of the layout comprising multi-level hierarchical layouts.

38. The electronic data signal of

claim 30

, wherein the layout verification operations and the optical process correction (OPC) operations are performed on a set of edges the represent portions of the integrated device layout.

39. The electronic data signal of

claim 30

, wherein the integrated device design comprises an integrated circuit (IC) layout.

40. An integrated verification and manufacturability tool, comprising:

a database in which is stored shared data to create a device via a lithographic process;

a number of integrated software tools that analyze the shared data in the database to confirm the manufacturability of the device; and

an integrated tool that converts the shared data into a mask writing language that is exported to a mask writer in order to create one or more lithographic masks to be used in the lithographic process.

41. The integrated verification and manufacturability tool of

claim 40

, wherein the mask writing language provides data to raster scanning mask writing tools.

42. The integrated verification and manufacturability tool of

claim 40

, wherein the mask writing language provides data to vector scan mask writing tools.

43. The integrated verification and manufacturability tool of

claim 40

, wherein the mask writing language provides data to a parallel array of mask writing elements.

44. The integrated verification and manufacturability tool of

claim 42

, in which the parallel mask writing elements are an array of microscopic mirrors.

45. The integrated verification and manufacturability tool of

claim 42

, in which the parallel mask writing elements are independently modulated laser beams.

46. The integrated verification and manufacturability tool of

claim 42

, in which the parallel mask writing elements are an array of scanning probe microscope elements.

47. The integrated verification and manufacturability tool of

claim 40

, wherein the mask writing language retains a portion of the hierarchical structure of the database.

48. The integrated verification and manufacturability tool of

claim 40

, wherein the mask writing language produces data that has no hierarchy and is flat.