FULL TIME OPERATING SYSTEM

• US 20010054056A1
• Filed: 09/11/1997
• Published: 12/20/2001
• Est. Priority Date: 09/11/1997
• Status: Active Grant

• Current Assignee: International Business Machines Corporation, Nisshinbo Industries, Inc. (Kawasaki Heavy Industries Limited)
• Original Assignee: International Business Machines Corporation
• Inventors: VENTRONE, SEBASTIAN
• Granted Patent: US 6,405,234 B2
• Time in Patent Office: Days
• US Class Current: 718/102
• CPC Class Codes: G06F 9/46 Multiprogramming arrangements
• CPC Class Codes: G06F 9/462 with multiple register sets

Abstract

A processing system executing multiple programs and operating under control of an operating system, comprising a processor unit which includes a dispatch/decode unit under control of the operating system for dispatching and decoding instructions of the multiple programs, the instructions each including a program ID. The processor unit further comprises a plurality of execution units, each separately selectable by the operating system for receiving any of the instructions of the multiple programs from the dispatch/decode unit, wherein one of the execution units is executing an instruction from one of the multiple programs while another of the execution units is executing an instruction from another one of the multiple programs. The processor unit also comprises a retirement unit storing results of executed ones of the instructions uniquely in response to each program ID.

Claims

1. A processing system executing multiple programs and operating under control of an operating system, the processor system comprising:

a processor unit including;

a dispatch/decode unit under control of the operating system for dispatching and decoding instructions of the multiple programs, the instructions each including a data ID;

a plurality of execution units, each separately selectable by the operating system for receiving any of the instructions of the multiple programs from the dispatch/decode unit, wherein one of the execution units is executing an instruction from one of the multiple programs while another of the execution units is executing an instruction from another one of the multiple programs; and

a retirement unit storing results of executed ones of the instructions uniquely in response to each data ID.

2. The processing system of

claim 1

wherein the operating system is resident in the processor unit.

3. The processing system of

claim 1

wherein the processor unit further comprises at least one dedicated operating system instruction set register.

4. The processor system of

claim 3

wherein the operating system instruction set register uses a tagging means to track the status of each instruction.

5. The processing system of

claim 1

wherein the operating system further comprises means for resetting any register within the processor unit.

6. The processing system of

claim 1

wherein the operating system further comprises means for granting non-symmetrical access to the processor unit and other processing system resources.

7. Instruction execution architecture of an information handling system comprising:

an operating system that can run continuously, even during execution of multiple tasks;

at least one program address register;

at least one memory control register; and

at least one task ID per task.

8. The architecture of

claim 7

wherein the operating system is resident in a central processing unit.

9. The architecture of

claim 7

, further comprising at least one dedicated operating system instruction set register.

10. The architecture of

claim 9

wherein the operating system instruction set register uses a tagging means to track the status of each task.

11. The architecture of

claim 7

wherein the operating system further comprises means for resetting any register.

12. The architecture of

claim 7

wherein the operating system further comprises means for granting non-symmetrical access to resources of the information handling system.