DISCRETE DEVICES INCLUDING EAPROM TRANSISTOR AND NVRAM MEMORY CELL WITH EDGE DEFINED FERROELECTRIC CAPACITANCE, METHODS FOR OPERATING SAME, AND APPARATUS INCLUDING SAME
First Claim
1. A one transistor/one capacitor (1T/1C) memory cell comprising a ferroelectric capacitor operatively coupled to the gate electrode of a charge amplifier transistor.
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Accused Products
Abstract
A memory cell includes a charge amplifier having a gate adjacent to a channel region coupling source and drain regions, a digitline coupled to one of the source and drain regions, a ground lead coupled to the other of the source and drain regions, a ferroelectric capacitor coupled to the gate, and a wordline coupled to the ferroelectric capacitor. Advantageously, the charge amplifier can be a CMOS transistor. Preferably, the gate is coupled to the ferroelectric capacitor by polysilicon, the junction formed at the gate has an intrinsic capacitance, and the capacitance of the ferroelectric capacitor is based on the magnitude of the intrinsic capacitance. Alternatively, the gate is coupled to the ferroelectric capacitor by polysilicon, the junction formed at the gate has an intrinsic capacitance, and the physical size of the ferroelectric capacitor is based on the magnitude of the intrinsic capacitance. In this case, the thickness of a ferroelectric material layer in the ferroelectric capacitor can be based on the magnitude of the intrinsic capacitance. A memory cell array, a memory module, and a processor based system can all be fabricated from this memory cell. Methods for reading data out of and writing data into the memory cell are also described.
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Citations
56 Claims
- 1. A one transistor/one capacitor (1T/1C) memory cell comprising a ferroelectric capacitor operatively coupled to the gate electrode of a charge amplifier transistor.
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5. A memory cell comprising:
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a charge amplifier comprising a gate adjacent to a channel region coupling source and drain regions;
a digitline coupled to one of the source and drain regions;
a source line coupled to the other of the source and drain regions;
a ferroelectric capacitor coupled to the gate; and
a wordline coupled to the ferroelectric capacitor. - View Dependent Claims (6, 7, 8, 9, 10)
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11. A memory cell comprising:
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a charge amplifier comprising a gate opposing a channel region coupling source and drain regions;
a digitline coupled to the drain region;
a source line coupled to the source region;
a ferroelectric capacitor, which stores data; and
a wordline coupled to the gate by the ferroelectric capacitor. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 45)
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- 20. A one transistor/one capacitor (1T/1C) memory cell array, wherein each of the 1T/1C memory cells comprises a ferroelectric capacitor operatively coupled to the gate electrode of a charge amplifier transistor.
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26. A memory cell array, comprising:
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a plurality of memory cells organized as an array of rows and columns, at least one of the memory cells being a non-volatile memory cell comprising;
a charge transistor comprising a gate opposing a channel region coupling source and drain regions;
a digitline coupled to the drain region;
a source line coupled to the source region, a ferroelectric capacitor coupled to the gate;
a wordline coupled to the ferroelectric capacitor; and
a sense amplifier coupled to the digitline of the at least one memory cell. - View Dependent Claims (27, 28, 29, 30, 31, 32, 33, 34)
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35. A processor based system, comprising:
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a processor; and
a memory cell array coupled to the processor, the memory cell array including a plurality of memory cells organized as an array of rows and columns, at least one of the memory cells being a non-volatile memory cell comprising;
a charge amplifier comprising a gate opposing a channel region coupling source and drain regions;
a digitline coupled to the drain region;
a source line coupled to the source region;
a ferroelectric capacitor coupled to the gate;
a wordline coupled to the ferroelectric capacitor; and
a sense amplifier coupled to the digitline of the at least one memory cell. - View Dependent Claims (36, 37, 38, 39, 40)
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41. A memory module, comprising:
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a substrate;
a plurality of memory chips mounted on the substrate, wherein one or more of the memory chips comprise a memory cell array fabricated on a semiconductor chip and communicating with a processor, said memory cell array comprising at least on non-volatile memory cell comprising a ferroelectric capacitor operatively coupled to the gate of a charge amplifier. - View Dependent Claims (42, 43, 44, 46)
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48. A method for reading information from a one transistor/one capacitor (1T/1C) memory cell having a charge amplifier including a gate disposed adjacent to a channel region coupling source and drain regions, a digitline coupled to drain region, a source line coupled to the source region, a ferroelectric capacitor coupled to the gate, and a wordline coupled to the ferroelectric capacitor, the method comprising:
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grounding the source line;
asserting the wordline and digitline;
amplifying the charge on the ferroelectric capacitor; and
determining the resultant charge on the digitline. - View Dependent Claims (49, 50)
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51. A method for writing information to a one transistor/one capacitor (1T/1C) memory cell having a charge amplifier including a gate disposed adjacent to a channel region coupling source and drain regions, a digitline coupled to drain region, a source line coupled to the source region, a ferroelectric capacitor coupled to the gate, and a wordline coupled to the ferroelectric capacitor, the method comprising:
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asserting the source line; and
asserting the wordline to thereby apply a potential greater than the coercive voltage of the ferroelectric capacitor across the ferroelectric capacitor and the charge amplifier. - View Dependent Claims (52)
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53. A logic element, comprising:
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N+1 source/drain regions;
N channels, each channel coupling adjacent ones of the N+1 source/drain regions;
N gates disposed adjacent to the N channels;
N ferroelectric capacitors, each of the N ferroelectric capacitors coupled to a respective one of the N gates;
a digitline couple to an end one of the N+1 source/drain regions; and
a source line coupled to the other end one of the N+1 source/drain regions. - View Dependent Claims (54, 55, 56)
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Specification