SYSTEM AND METHOD FOR SYNCHRONIZING DISPARATE PROCESSING MODES AND FOR CONTROLLING ACCESS TO SHARED RESOURCES

• US 20020004810A1
• Filed: 04/01/1997
• Published: 01/10/2002
• Est. Priority Date: 04/01/1997
• Status: Active Grant

• Current Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Original Assignee: Microsoft Corporation
• Inventors: RENERIS, KENNETH S.
• Granted Patent: US 6,343,338 B1
• Time in Patent Office: Days
• US Class Current: 718/104
• CPC Class Codes: G06F 9/526 Mutual exclusion algorithms

Abstract

A system and method for synchronizing disparate processing modes and for providing mutually exclusive access to shared system resources. A processing unit operates in disparate first and second processing modes. In the first processing mode, the computer is under the control of an operating system. In the other processing mode, the computer is under the control of a system management mode interrupt handling routine. To synchronize the two processing modes and allow mutually exclusive access to shared hardware resources, the computer system includes shared memory, which contains an intermodal lock, and a mechanism for allowing each processing mode to signal the other. Before either processing mode can access the shared resource, the processing mode must attempt to acquire the intermodal lock. If the lock is acquired, the processing mode accesses the shared resource. If the lock cannot be acquired, the processing mode sets a pending bit and resumes other tasks until it receives a lock release signal from the other processing mode. When a processing mode has finished accessing the shared resource, it releases the lock and checks to see if the pending bit was set. If so, the processing mode sends a lock release signal to the other mode.

Claims

1. A method for synchronizing first and second processing modes executed by a processing unit and for controlling access to a shared resource, comprising the steps of:

providing a lock for controlling access to the shared resource, the lock being accessible to the first and second processing modes;

attempting, from the first processing mode, to acquire the lock;

if the lock is acquired by the first processing mode, accessing the shared resource from the first processing mode;

releasing the lock after accessing the shared resource from the first processing mode;

determining whether the second processing mode has requested the lock; and

if the second processing mode has requested the lock, sending a release signal to the second processing mode.

2. The method recited in claim 1, further comprising the steps of:

if the lock is not acquired by the first processing mode, setting a pending indicator; and

in response to a signal from the second processing mode, again attempting to acquire the lock from the first processing mode.

3. The method recited in claim 2, wherein the signal from the second processing mode is sent to the first processing mode in response to the pending indicator being set by the first processing mode.

4. The method recited in claim 1, wherein the lock comprises a register accessible to the first and second processing modes.

5. The method recited in claim 1, wherein the step of attempting to acquire the lock comprises the steps of:

reading a value in a data register associated with the lock;

retaining an original lock value comprising the read value;

retaining an altered lock value comprising the read value with an owned bit set;

determining whether the original lock value'"'"'s owned bit was set;

if the original lock value'"'"'s owned bit was set, setting the altered lock value'"'"'s pending bit;

determining whether the value in the data register remains equal to the original lock value; and

if the value in the data register remains equal to the original lock value, storing the altered lock value in the data register.

6. The method recited in claim 5, wherein the steps of determining whether the value in the data register remains equal to the original lock value and storing the altered lock value in the data register constitute an atomic operation.

7. The method recited in claim 5, further comprising the step of returning, if the altered lock value'"'"'s pending bit was set, a value indicating the lock was not acquired, otherwise, returning a value indicating the lock was acquired.

8. The method recited in claim 1, wherein the step of releasing the lock comprises the steps of:

reading a value in a data register associated with the lock;

retaining an original lock value comprising the read value;

retaining an altered lock value comprising the read value with the owned bit and pending bit cleared;

determining whether the value in the data register remains equal to the original lock value; and

if the value in the data register remains equal to the original lock value, storing the altered lock value in the data register.

9. The method recited in claim 8, wherein the steps of determining whether the value in the data register remains equal to the original lock value and storing the altered lock value in the data register constitute an atomic operation.

10. The method recited in claim 1, wherein the step of sending a release signal to the second processing mode comprises generating an interrupt to the second processing mode.

11. A computer system, comprising:

a processing unit capable of executing first and second processing modes;

a shared resource accessible to the first and second processing modes; and

a lock for controlling access to the shared resource, the lock including a lock data register accessible to the first and second processing modes;

the processing unit, responsive to instructions from a program module running on the computer system, being operative to;

attempt, from the first processing mode, to acquire the lock;

access the shared resource from the first processing mode if the lock is acquired by the first processing mode, otherwise, set a pending indicator associated with the lock;

release the lock after accessing the shared resource from the first processing mode;

determine, after accessing the shared resource from the first processing mode, whether the second processing mode has attempted to acquire the lock; and

if the second processing mode has attempted to acquire the lock, send a signal to the second processing mode.

12. The computer system recited in claim 11, wherein the processor is further operative to:

read a value in the lock data register;

store the value in first and second registers;

set an owned bit in the second register;

determine whether an owned bit in the first register was set;

if the owned bit in the first register was set, set a pending bit in the second register;

determine whether the value in the lock data register remains equal to the value stored in the first register; and

if the value in the lock data register remains equal to the value stored in the first register, store the value in the second register in the lock data register,

wherein determining whether the value in the lock data register remains equal to the value stored in the First register and storing the value from the second register in the lock data register constitute an atomic operation.

13. The computer system recited in claim 11, wherein the processor is further operative to return, if a pending bit in the second register was set, a value indicating the lock was not acquired, otherwise, to return a value indicating the lock was acquired.

14. The computer system recited in claim 11, wherein the processor is further operative to:

read a value in the lock data register;

store the value in first and second registers;

clear an owned bit in the second register;

clear a pending bit in the second register;

determine whether the value in the lock data register remains equal to the value stored in the first register; and

if the value in the lock data register remains equal to the value stored in the first register, store the value in the second register in the lock data register.

15. The computer system recited in claim 11, wherein sending a signal to the second processing mode comprises generating an interrupt to the second processing mode.

16. A computer-readable medium on which is stored a computer program for synchronizing first and second processing modes executed by a processing unit and for controlling access to a shared resource, the computer program comprising instructions which, when executed by the processing unit, perform the steps of:

providing a lock for controlling access to the shared resource, the lock including a register accessible to the first and second processing modes and indicating the availability of access to the shared resource;

attempting, from the first processing mode, to acquire the lock;

if the lock is acquired by the first processing mode, accessing the shared resource from the first processing mode;

releasing the lock after accessing the shared resource from the first processing mode;

determining whether the second processing mode has attempted to acquire the lock; and

if the second processing mode has attempted to acquire the lock, sending a signal to the second processing mode.

17. The computer-readable medium recited in claim 16, wherein the computer program further comprises instructions which, when executed by the computer, perform the steps of:

if the lock is not acquired by the first processing mode, setting a pending indicator;

sending a signal from the second processing mode to the first processing mode in response to the pending indicator being set by the first processing mode; and

in response to the signal from the second processing mode, again attempting, from the first processing mode, to acquire the lock.

18. The computer-readable medium recited in claim 16, wherein attempting to acquire the lock comprises the steps of:

reading a value in the register;

retaining an original lock value comprising the read value;

retaining an altered lock value comprising the read value with an owned bit set;

determining whether the owned bit was set in the original lock value;

if the owned bit in the original lock value was set, setting a pending bit in the altered lock value;

determining whether the value in the register remains equal to the original lock value; and

if the value in the register remains equal to the original lock value, storing the altered lock value in the register.

19. The computer-readable medium recited in claim 18, wherein the steps of determining whether the value in the register remains equal to the original lock value and storing the altered lock value in the register constitute an atomic operation.

20. The computer-readable medium recited in claim 18. wherein the computer program further comprises instructions which, when executed by the computer, perform the step of returning, if the altered lock value'"'"'s pending bit was set, a value indicating the lock was not acquired, otherwise, returning a value indicating the lock was acquired.

21. The computer-readable medium recited in claim 16, wherein releasing the lock comprises the steps of:

reading a value in the register;

retaining an original lock value comprising the read value;

retaining an altered lock value comprising the read value with the owned bit and pending bit cleared;

determining whether the value in the register remains equal to the original lock value; and

if the value in the register remains equal to the original lock value, storing the altered lock value in the register.