Multiple stream variable length encoder and decoder
First Claim
1. An apparatus comprises:
- a first plurality of registers, each register in the first plurality of registers configured to store data packets;
a first selector coupled to the first plurality of registers, the first selector configured to receive a data packet stored in each register in the first plurality of registers, and configured to output the data packet from a selected register from the first plurality of registers in response to a selection signal;
a second plurality of registers, each register in the second plurality of registers configured to store a pointer associated with each register in the first plurality of registers;
a second selector coupled to the second plurality of registers, the selector circuit configured to receive data from each register in the second plurality of registers, and configured to output data from a selected register from the second plurality of registers in response to the selection signal, the data comprising a pointer associated with the selected register from the first plurality of registers;
a shifter coupled to the first selector and to the second selector circuit, the shifter configured to receive the data packet from the selected register in the first plurality of registers, configured to receive the pointer, and configured to output a portion of the data packet, the portion of the data packet determined by the pointer; and
a decoder coupled to the shifter, the decoder configured to receive the portion of the data packet, and configured to output decoded data in response to the portion of the data packet.
1 Assignment
0 Petitions
Accused Products
Abstract
An apparatus may include a first plurality of registers, each register in the first plurality of registers configured to store data wordss, a first selector coupled to the first plurality of registers, the first selector configured to receive a data words stored in each register in the first plurality of registers, and configured to output the data words from a selected register from the first plurality of registers in response to a selection signal, a second plurality of registers, each register in the second plurality of registers configured to store a pointer associated with each register in the first plurality of registers, a second selector coupled to the second plurality of registers, the selector circuit configured to receive data from each register in the second plurality of registers, and configured to output data from a selected register from the second plurality of registers in response to the selection signal, the data comprising a pointer associated with the selected register from the first plurality of registers, a shift register coupled to the first selector and to the second selector circuit, the shift register configured to receive the data words from the selected register in the first plurality of registers, configured to receive the pointer, and configured to output a portion of the data words, the portion of the data words determined by the pointer, and a decoder coupled to the shift register, the decoder configured to receive the portion of the data words, and configured to output decoded data in response to the portion of the data words.
-
Citations
21 Claims
-
1. An apparatus comprises:
-
a first plurality of registers, each register in the first plurality of registers configured to store data packets;
a first selector coupled to the first plurality of registers, the first selector configured to receive a data packet stored in each register in the first plurality of registers, and configured to output the data packet from a selected register from the first plurality of registers in response to a selection signal;
a second plurality of registers, each register in the second plurality of registers configured to store a pointer associated with each register in the first plurality of registers;
a second selector coupled to the second plurality of registers, the selector circuit configured to receive data from each register in the second plurality of registers, and configured to output data from a selected register from the second plurality of registers in response to the selection signal, the data comprising a pointer associated with the selected register from the first plurality of registers;
a shifter coupled to the first selector and to the second selector circuit, the shifter configured to receive the data packet from the selected register in the first plurality of registers, configured to receive the pointer, and configured to output a portion of the data packet, the portion of the data packet determined by the pointer; and
a decoder coupled to the shifter, the decoder configured to receive the portion of the data packet, and configured to output decoded data in response to the portion of the data packet. - View Dependent Claims (2, 3, 4, 6, 7)
-
-
5. The apparatus of claim
wherein the portion of the data packet is encoded in a Huffman encoding scheme; - and
wherein the decoder is configured to decode Huffman encoded data.
- and
-
8. A method for decoding streams of encoded data comprises:
-
receiving a first stream of encoded data, the first stream from a first source;
receiving a second stream of encoded data, the second stream from a second source;
storing a first set of data in a first register, the first set of data from the first stream of encoded data;
storing a second set of data in a second register, the second set of data from the second stream of encoded data;
storing a first pointer in a third register, the first pointer associated with the first set of data;
storing a second pointer in a fourth register, the second pointer associated with the second set of data;
applying a first signal to a selector;
when the first signal is applied to the selector, coupling the first register and the third register to a shifter, and outputting data with the shifter, the data comprising a portion of the first set of data in response to the first pointer;
when the first signal is not applied to the selector, coupling the second register and the fourth register to the shifter, and outputting data with the shifter, the data comprising a portion of the second set of data in response to the second pointer; and
decoding the data from the shifter and outputting decoded data. - View Dependent Claims (9, 10, 11, 12, 13)
-
-
14. An encoding apparatus configured to receive data input from data sources and offsets associated with the data sources comprises
a first plurality of registers, each register in the first plurality of registers configured to store data wordss; -
a first selector coupled to the first plurality of registers, the first selector configured to receive a data words stored in each register in the first plurality of registers, and configured to output the data words from a selected register from the first plurality of registers in response to a selection signal;
a second plurality of registers, each register in the second plurality of registers configured to store a pointer;
a second selector coupled to the second plurality of registers, the selector circuit configured to receive data from each register in the second plurality of registers, and configured to output data from a selected register from the second plurality of registers in response to the selection signal, the data comprising pointers associated with the data sources;
an accumulator coupled to the second selector, the accumulator configured to combine the pointers associated with the data sources and the offsets;
a shift register coupled to the accumulator, the shift register configured to receive the data input, configured to receive output from the accumulator, and configured to output the data input at a shifted position in response to the output from the accumulator; and
a logic circuit coupled to the shift register and to the first selector, the logic circuit configured to perform a logic function on the data words from the selected register and output from the shift register;
wherein the first plurality of registers is also coupled to the logic circuit and the first plurality of registers is configured to store output from the logic circuit. - View Dependent Claims (15, 16, 17, 18, 19, 20, 21)
-
Specification