Pixel layout for CMOS image sensor

• US 20020008767A1
• Filed: 02/08/2001
• Published: 01/24/2002
• Est. Priority Date: 02/11/2000
• Status: Active Grant

• Current Assignee: Intellectual Ventures II LLC (Intellectual Ventures LLC)
• Original Assignee: Hyundai Electronics Industries Co. Ltd. (SK Hynix Inc.)
• Inventors: Lee, Do-Young
• Granted Patent: US 7,057,656 B2
• Time in Patent Office: Days
• US Class Current: 348/308
• CPC Class Codes: H01L 27/14603 Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/14627 Microlenses
• CPC Class Codes: H01L 27/14645 Colour imagers
• CPC Class Codes: H04N 25/00 Circuitry of solid-state image sensors [SSIS]; Control thereof

Abstract

A novel CMOS image unit pixel layout having a photodiode including an optically optimized square image sensing region. The square image sensing layout provides for reduced electrical and color crosstalk and improved modulation transfer function (MTF) between neighboring pixels of an array of pixels.

Claims

1. A CMOS pixel for use in a CMOS imager, comprising:

.

a. a photodiode having a substantially square-shaped image sensing area, an anode coupled to ground and a cathode;

b. a transfer transistor having a drain coupled to the cathode of the photodiode, a gate controlled by a control signal, Tx, and a source coupled to a floating sensing node;

c. a reset transistor having a drain coupled to a reset potential, a gate controlled by a control signal, Rx, and a source coupled to the floating sensing node; and

d. a source follower coupled between the floating node and an output of the unit pixel, the source follower controlled by a select signal.

2. The CMOS pixel of claim 1, wherein the source transistor, reset transistor and source follower are positioned along at least two sides of the image sensing area.

3. The CMOS pixel of claim 1, further comprising a substantially hemispherically-shaped microlense positioned substantially over the image sensing area.

4. An array of CMOS pixels, each pixel comprising a substantially square image sensing region, wherein a distance between the image sensing regions of neighboring pixels is optimized to reduce crosstalk between the neighboring pixels.

5. The array of pixels of claim 4, wherein the distance is further optimized to improve MTF.

6. An improved CMOS imaging array for use in a CMOS imaging system, the improvement comprising:

using a substantially square image sensing region within each pixel to reduce the distance between the image sensing regions of neighboring pixels.

7. The CMOS imaging array of claim 6, further comprising:

a microlense, positioned over the image sensing area of each pixel to increase the effective fill factor.

8. The CMOS imaging array of claim 7, wherein each pixel comprises:

a. a transfer transistor having a drain coupled to the cathode of the photodiode, a gate controlled by a control signal, Tx, and a source coupled to a floating sensing node;

b. a reset transistor having a drain coupled to a reset potential, a gate controlled by a control signal, Rx, and a source coupled to the floating sensing node; and

c. a source follower coupled between the floating node and an output of the unit pixel, the source follower controlled by a select signal.