GATE INSULATOR PROCESS FOR NANOMETER MOSFETS

• US 20020009855A1
• Filed: 04/07/1999
• Published: 01/24/2002
• Est. Priority Date: 04/07/1999
• Status: Active Grant

• Current Assignee: Lattice Semiconductor Corporation
• Original Assignee: Lattice Semiconductor Corporation
• Inventors: KIM, HYEON-SEAG
• Granted Patent: US 6,413,826 B2
• Time in Patent Office: Days
• US Class Current: 438/278
• CPC Class Codes: H01L 21/823462 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure

Abstract

Methods of manufacturing insulating materials and semiconductor devices incorporating films having high dielectric constants are disclosed, in which the high-dielectric constant material is deposited on a semiconductor surface that has been treated to prevent the formation of interfacial oxide between the semiconductor substrate and the high dielectric constant material. The methods of this invention involve implantation of nitrogen ions through the sacrificial oxide layer, thereby forming a nitrided silicon substrate underneath the sacrificial oxide. The sacrificial oxide can then removed, and thereafter layers of high dielectric constant materials can be deposited on the nitrided silicon substrate without the formation of interfacial oxide. Manufacturing devices using the methods of this invention can result in the formation of an overall insulating film having a dielectric constant that more closely reflects the dielectric constant of the high-dielectric constant material. Therefore, the insulating films made using the methods of this invention can be made thinner than conventional insulating films, thus permitting the manufacture of semiconductor products having increasing device density and increasing efficiency, and decreasing manufacturing costs.

Claims

1. A method for forming a semiconductor insulating layer, comprising the steps of:

providing a semiconductor wafer having a silicon substrate and having a layer of sacrificial oxide thereon;

implanting nitrogen ions through said sacrificial oxide layer and into said silicon substrate;

removing said sacrificial oxide layer; and

depositing a layer of high-dielectric constant insulating material on said implanted nitrided silicon substrate.

2. The method of claim 1, wherein after said step of providing a semiconductor wafer, further comprising the steps of

forming a patterned barrier layer on said sacrificial oxide layer;

and

forming shallow trenches.

3. The method of claim 2, wherein after the step of implanting further comprising the step of filling said shallow trenches with an insulating material.

4. The method of claim 3, wherein after the step of deposition said layer of high dielectric constant insulating material, further comprising forming a gate structure on said high-dielectric constant insulating material.

5. The method of claim 1, wherein said step of implanting nitrogen ions comprises using ion beam implantation.

6. The method of claim 5, wherein said ion beam implantation is carried out using an energy in the range of about 5 KeV to about 50 KeV.

7. The method of claim 5, wherein said ion beam implantation implants nitrogen ions in a concentration in the range of about 10¹³ ions/cm³ to about 10¹⁸ ions/cm.

8. The method of claim 5, wherein said ion beam implantation implants nitrogen ions at a dose of about 10¹³ ions/cm² to about 10¹⁵ ions/cm².

9. The method of claim 1, wherein the high-dielectric constant insulating layer comprises a material having a dielectric constant in the range of greater than about 4 to about 200.

10. The method of claim 1, wherein the high-dielectric constant insulating layer comprises a material selected from the group consisting of Ta₂O₅, Al₂O₃, Si₃N₄, ZrO₂, TiO₂, barium-strontium-titanium oxide and lead-zirconium-titanium oxide.

11. The method of claim 1, wherein the depth of said nitrided silicon substrate is in the range of about 1 Å

to about 1500 Å

.

12. The method of claim 1, wherein said step of removing said oxide layer is carried out by etching.

13. The method of claim 1, wherein said semiconductor wafer has at least two regions, each of said regions having a layer of sacrificial oxide thereon, and wherein nitrogen ion implantation is carried out in one region of said semiconductor wafer, and nitrogen ion implantation is not carried out in another of said regions of said semiconductor wafer.

14. The method of claim 1, further comprising the step of forming a layer of conductive material on the surface of the high dielectric constant insulating material.

15. The method of claim 14, wherein said conductive material is selected from the group consisting of polysilicon, platinum, WSi, Co, TiN₂ and RuO₂.

25. The method of claim 1, further comprising the step of forming a layer of conductive material on the surface of the high dielectric constant insulating material.

26. The method of claim 14, wherein said conductive material is selected from the group consisting of polysilicon, platinum, WSi, Co, TiN₂ and RuO₂.

16. A method for manufacturing a semiconductor device, comprising the steps of:

providing a semiconductor wafer comprising a silicon substrate having a layer of sacrificial oxide thereon;

forming shallow trenches on said wafer;

filling said trenches with an oxide insulating material thereby forming field oxide regions;

implanting nitrogen ions through said sacrificial oxide, thereby forming an implanted nitrided silicon substrate;

removing said sacrificial oxide; and

forming gate insulators between said field oxide regions.

17. The method of claim 16, wherein said step of implantation nitrogen ions comprises using ion beam implantation.

18. The method of claim 17, wherein said step of ion beam implantation is carried out at an energy in the range of about 5 KeV to about 50 KeV.

19. The method of claim 17, wherein said ion beam implantation implants nitrogen ions in a concentration in the range of about 10¹³ to about 10¹⁸ ions/cm³.

20. The method of claim 17, wherein said ion beam implantation implants nitrogen ions at a dose in the range of about 10¹³ ions/cm² to about 10¹⁵ ions/cm².

21. The method of claim 16, wherein said step of forming gate insulators comprises deposition of an insulating material having a high dielectric constant.

22. The method of claim 21, wherein said insulating material has a dielectric constant in the range of about 4 to about 200.

23. The method of claim 21, wherein the high-dielectric constant insulating layer comprises a material selected from the group consisting of Ta₂O₅, Al₂O₃, Si₃N₄, ZrO₂, TiO₂, barium-strontium-titanium oxide and lead-zirconium-titanium oxide.

24. The method of claim 16, wherein the depth of said nitrided silicon substrate is in the range of about 1 Å

to about 1500 Å

.