Emulated branch effected by trampoline mechanism

• US 20020010851A1
• Filed: 03/08/2000
• Published: 01/24/2002
• Est. Priority Date: 10/13/1997
• Status: Active Grant

• Current Assignee: Institute For The Development of Emerging Architectures LLC
• Original Assignee: Institute For The Development of Emerging Architectures LLC
• Inventors: Hays, James O., Morris, Dale C., Ross, Jonathan K., Huck, Jerome C.
• Granted Patent: US 6,505,296 B2
• Time in Patent Office: Days
• US Class Current: 712/244
• CPC Class Codes: G06F 11/1407 Checkpointing the instruction stream
• CPC Class Codes: G06F 8/445 Exploiting fine grain parallelism, i.e. parallelism at instruction level run-time instruction scheduling G06F9/3836
• CPC Class Codes: G06F 9/3834 Maintaining memory consistency
• CPC Class Codes: G06F 9/3838 Dependency mechanisms, e.g. register scoreboarding
• CPC Class Codes: G06F 9/3842 Speculative instruction execution
• CPC Class Codes: G06F 9/3861 Recovery, e.g. branch miss-prediction, exception handling error detection or correction G06F11/00

Abstract

A computer system includes a processor for executing a program and an interruption handler from a memory. The processor includes an instruction pointer indicating a memory location of a current executing instruction. The processor executes a trampoline check instruction in the program which tests a condition and if the condition is true, causes an interruption and supplies an address displacement. The interruption handler responds to the interruption and restarts execution of the program at a restart point indicating a memory location of a special handler in the program. The restart point is a sum of the address displacement and a value of the instruction pointer at the time of the interruption. If the condition is false, normal control flow of the program is continued.

Claims

1. A computer system comprising:

memory storing a program and an interruption handler, wherein the program has instructions including a trampoline check instruction and a special handler for handling an interruption; and

a processor for executing the program and the interruption handler, wherein the processor includes an instruction pointer indicating a memory location of a current executing instruction, wherein the processor executes the trampoline check instruction which tests a condition and if the condition is true, causes the interruption and supplies an address displacement, wherein the interruption handler responds to the interruption and restarts execution of the program at a restart point indicating a memory location of the special handler, wherein the restart point is equal to a sum of the address displacement and a value of the instruction pointer at the time of the interruption.

2. The computer system of claim 1 wherein the interruption handler adds the address displacement to the value of the instruction pointer at the time of the interruption to obtain the restart point in response to the interruption.

3. The computer system of claim 1 wherein the processor includes hardware for adding the address displacement to the value of the instruction pointer at the time of the interruption to obtain the restart point and an interruption control register for capturing the restart point, wherein the interruption handler obtains the restart point from the interruption control register in response to the interruption.

4. The computer system of claim 1 wherein the processor further includes an interruption control register for capturing the address displacement.

5. The computer system of claim 1 wherein the memory further stores an interruption vector table including an interruption vector for supplying information related to the interruption.

6. The computer system of claim 5 wherein the interruption vector is not shared with other interruptions.

7. The computer system of claim 1 wherein the processor executes the special handler of the program to handle the interruption.

8. The computer system of claim 7 wherein after the special handler handles the interruption, the processor executes a branch instruction to branch back to a portion of the program that was executing at the time of the interruption.

9. The computer system of claim 1 wherein if the condition is false, normal control flow of the program is continued.

10. The computer system of claim 1 wherein the memory stores an operating system for controlling the processor and the memory and wherein the interruption handler is part of the operating system.

11. The computer system of claim 1 wherein the program instructions further include:

a store instruction;

a load instruction that is scheduled before the store instruction; and

wherein the condition is true if the store instruction and the load instruction access a common location in the memory.

12. The computer system of claim 11 wherein the special handler comprises recovery code including code for re-execution of the load instruction.

13. The computer system of claim 11 wherein the program instructions further include:

at least one calculation instruction that is dependent on data read by the load instruction, the at least one calculation instruction being scheduled ahead of the store instruction.

14. The computer system of claim 13 wherein the special handler comprises recovery code including code for re-execution of the load instruction and the at least one calculation instruction.

15. The computer system of claim 1 wherein the program instructions further include a first instruction and a second instruction, wherein the second instruction is scheduled ahead of the first instruction, and wherein the condition is true if the second instruction operates upon data that is dependent upon the execution of the first instruction.

16. The computer system of claim 15 wherein the special handler comprises recovery code including code for re-execution of the second instruction.

17. The computer system of claim 1 wherein the program instructions further include at least one instruction marked as speculative, and wherein the condition is true if integrity of execution of the at least one instruction marked as speculative is not verified.

18. The computer system of claim 17 wherein the special handler comprises recovery code including code for re-execution of the at least one instruction marked as speculative.

19. The computer system of claim 1 wherein the program instructions are organized in a plurality of basic blocks, each basic block including a set of contiguous instructions, and the program instructions including;

a first instruction that is associated with a first basic block and is capable of generating an exception during execution of the program, wherein the first instruction is scheduled outside of the first basic block and ahead of at least one instruction that precedes the first basic block; and

wherein the condition is true if the first instruction generated an exception.

20. The computer system of claim 19 wherein the trampoline check instruction is scheduled within the first basic block.

21. The computer system of claim 19 wherein the special handler comprises recovery code including code for re-execution of the first instruction.

22. The computer system of claim 1 wherein the program instructions further include:

a first speculative instruction that is capable of experiencing an instruction exception condition during execution of the first speculative instruction;

wherein the first speculative instruction defers signaling an instruction exception when the instruction exception condition is initially detected and completes execution without signaling the instruction exception;

wherein the condition is true if the instruction exception was detected during execution of the first speculative instruction.

23. The computer system of claim 22 wherein the special handler comprises recovery code including code for re-execution of the first speculative instruction.

24. A method of executing instructions in a computer system, the method comprising:

executing a program having instructions including a trampoline check instruction and a special handler for handling an interruption;

executing the trampoline check instruction including;

testing a condition; and

if the condition is true, causing the interruption and supplying an address displacement; and

executing an interruption handler in response to the interruption including;

restarting execution of the program at a restart point indicating a memory location of the special handler, wherein the restart point is equal to a sum of the address displacement and a value of an instruction pointer at the time of the interruption, wherein the instruction pointer indicates a memory location of a current executing instruction.

25. The method of claim 24 wherein the step of executing the interruption handler in response to the interruption includes:

adding the address displacement to the value of the instruction pointer at the time of the interruption to obtain the restart point.

26. The method of claim 24 further comprising:

adding, with hardware, the address displacement to the value of the instruction pointer at the time of the interruption to obtain the restart point;

capturing the restart point in an interruption control register; and

wherein the step of executing the interruption handler in response to the interruption includes;

obtaining the restart point from the interruption control register.

27. The method of claim 24 further comprising the step of:

capturing the address displacement in an interruption control register.

28. The method of claim 24 further comprising the step of:

supplying information related to the interruption with an interruption vector.

29. The method of claim 28 wherein the interruption vector is not shared with other interruptions.

32. The method of claim 24 wherein the step of executing the trampoline check instruction further includes:

if the condition is false, continuing normal control flow of the program.

33. The method of claim 24 wherein the step of executing the program further includes:

executing a store instruction;

executing a load instruction that is scheduled before the store instruction; and

wherein the condition is true if the store instruction and the load instruction access a common location in the memory.

34. The method of claim 33 wherein the special handler comprises recovery code and executing the recovery code includes re-executing the load instruction.

35. The method of claim 33 wherein the step of executing program instructions further includes:

executing at least one calculation instruction that is dependent on data read by the load instruction, the at least one calculation instruction being scheduled ahead of the store instruction.

36. The method of claim 35 wherein the special handler comprises recovery code and execution of the recovery code includes re-executing the load instruction and the at least one calculation instruction.

37. The method of claim 24 wherein executing the program instructions further includes:

executing a first instruction and a second instruction;

wherein the second instruction is scheduled ahead of the first instruction; and

wherein the condition is true if the second instruction operates upon data that is dependent upon the execution of the first instruction.

39. The method of claim 24 wherein executing the program instructions further includes:

executing at least one instruction marked as speculative; and

wherein the condition is true if integrity of execution of the at least one instruction marked as speculative is not verified.

40. The method of claim 39 wherein the special handler comprises recovery code and execution of the recovery code includes re-executing the at least one instruction marked as speculative.

41. The method of claim 24 wherein the program instructions are organized in a plurality of basic blocks, each basic block including a set of contiguous instructions, and executing the program instructions includes:

executing a first instruction that is associated with a first basic block and is capable of generating an exception during execution of the program;

wherein the first instruction is scheduled outside of the first basic block and ahead of at least one instruction that precedes the first basic block; and

wherein the condition is true if the first instruction generated an exception.

42. The method of claim 41 wherein the trampoline check instruction is scheduled within the first basic block.

43. The method of claim 41 wherein the special handler comprises recovery code and executing the recovery code includes re-executing of the first instruction.

44. The method of claim 24 wherein executing the program instructions further includes:

executing a first speculative instruction that is capable of experiencing an instruction exception condition during execution of the first speculative instruction including;

deferring signaling an instruction exception when the instruction exception condition is initially detected; and

completing execution without signaling the instruction exception; and

wherein the condition is true if the instruction exception was detected during execution of the first speculative instruction.

45. The method of claim 44 wherein the special handler comprises recovery code and executing the recovery code includes re-executing the first speculative instruction.

30. The method of 24 further comprising the step of:

executing the special handler of the program to handle the interruption.

31. The method of claim 30 further comprising the step of:

executing a branch instruction to branch back to a portion of the program that was executing at the time of the interruption.

38. The method of 37 wherein the special handler comprises recovery code and execution of the recovery code includes re-executing the second instruction.