Self aligned method of forming a semiconductor memory array of floating gate memory cells, and a memory array made thereby

• US 20020011608A1
• Filed: 10/05/2001
• Published: 01/31/2002
• Est. Priority Date: 09/22/1999
• Status: Active Grant

• Current Assignee: Silicon Storage Technology Incorporated (Microchip Technology Incorporated)
• Original Assignee: Silicon Storage Technology Incorporated (Microchip Technology Incorporated)
• Inventors: Lee, Dana
• Granted Patent: US 6,593,177 B2
• Time in Patent Office: Days
• US Class Current: 257/200
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A self aligned method of forming a semiconductor memory array of floating gate memory cells in a semiconductor substrate has a plurality of spaced apart isolation regions on the substrate substantially parallel to one another. An active region is between each pair of adjacent isolation regions. The active and isolation regions are formed in parallel and in the column direction. In the row direction, strips of spaced apart silicon nitride are formed. A source line plug is formed between adjacent pairs of silicon nitride and is in contact with a first region in the active regions, and the isolation regions. The strips of silicon nitride are removed and isotropically etched. In addition, the materials beneath the silicon nitride are also isotropically etched. Polysilicon spacers are then formed in the row direction parallel to the source line plug and adjacent to the floating gates. A second region is formed between adjacent, spaced apart, control gates. A bit line is formed in the bit line direction contacting the second region in the space between the control gates.

Claims

1. A self-aligned method of forming a semiconductor memory array of floating gate memory cells in a semiconductor substrate, each memory cell having a floating gate, a first terminal, a second terminal with a channel region therebetween, and a control gate, said method comprising the steps of:

a) forming a plurality of spaced apart isolation regions on said substrate, substantially parallel to one another in a first direction with an active region between each pair of adjacent isolation regions, said active region comprising a first layer of insulating material on said semiconductor substrate, and a first layer of polysilicon material on said first layer of insulating material;

b) forming a plurality of spaced apart masking regions of a masking material, substantially parallel to one another in a second direction on said active regions and isolation regions, said second direction substantially perpendicular to said first direction;

c) etching along said second direction under said masking material after the formation of a plurality of spaced apart masking regions of step (b);

d) forming a plurality of spaced apart first spacers of an insulating material, substantially parallel to one another in said second direction, each first spacer adjacent and contiguous to one of said masking regions with a first region between each pair of adjacent first spacers, each first spacer crossing a plurality of alternating active region and isolation region;

e) etching between pairs of adjacent first spacers in said first region;

f) forming the first terminal in said substrate in each of said active regions between pairs of adjacent first spacers in said first region;

g) forming a conductor in said second direction between each pairs of spaced apart first spacers electrically connected to the first terminal in said substrate;

h) removing said masking material resulting in a plurality of structures, substantially parallel to one another in the second direction;

i) forming an insulating film about each of said structures;

j) forming a plurality of spaced apart second spacers of a polysilicon material, substantially parallel to one another in said second direction each second spacer adjacent and contiguous to one of said structures, with a second region between each pair of adjacent second spacers, each second spacer crossing a plurality of alternating active region and isolation region, each of said second spacers being electrically connected control gates for memory cells in said second direction;

k) etching between pairs of adjacent second spacers in said second region;

l) forming the second terminal in said substrate in each of said active regions between pairs of adjacent second spacers in said second region; and

m) forming a conductor in a first direction, substantially parallel to an active region, electrically connected to the second terminal in said substrate.

2. The method of claim 1 wherein said forming step (a) forms said isolation regions and said first layer of polysilicon material in a self-aligned process.

3. The method of claim 1 wherein said forming step (a) forms said isolation regions and said first layer of polysilicon material in a non self-aligned process.

4. A self-aligned method of forming a semiconductor memory array of floating gate memory cells in a semiconductor substrate, each memory cell having a floating gate, a first terminal, a second terminal with a channel region therebetween, and a stack gate on said floating gate insulated and spaced apart therefrom, said method comprising the steps of:

a) forming a plurality of spaced apart isolation regions on said substrate, substantially parallel to one another in a first direction with an active region between each pair of adjacent isolation regions, said active region comprising a first layer of insulating material on said semiconductor substrate, and a first layer of polysilicon material on said first layer of insulating material;

b) depositing a second layer of insulating material on said active and isolation regions;

c) depositing a second layer of polysilicon material on said second layer of polysilicon material;

d) forming a plurality of spaced apart masking regions of a masking material, substantially parallel to one another in a second direction, on said second layer of polysilicon material, said second direction substantially perpendicular to said first direction;

e) forming a plurality of spaced apart first spacers of an insulating material, substantially parallel to one another in said second direction, each first spacer adjacent and contiguous to one of said masking regions with a first region between each pair of adjacent first spacers, each first spacer crossing a plurality of alternating active region and isolation region;

f) etching between pairs of adjacent first spacers in said first region;

g) forming the first terminal in said substrate in each of said active regions between pairs of adjacent first spacers in said first region;

h) forming a conductor in said second direction between each pairs of spaced apart first spacers electrically connected to the first terminal in said substrate;

i) removing said masking material, and anisotropically etching all material beneath said masking material to said substrate, resulting in a plurality of structures, substantially parallel to one another in the second direction;

j) forming an insulating film about each of said structures; and

k) forming a second terminal in said substrate in each side of said structures.

5. A semiconductor memory array of floating gate memory cells in a semiconductor substrate, each memory cell having a floating gate, a first terminal, a second terminal with a channel region therebetween, and a stack gate on said floating gate insulated and spaced apart therefrom, said array comprising:

a semiconductor substrate having a plurality of spaced apart active regions substantially parallel to one another in a first direction;

with an isolation region between each pair of active regions;

a plurality of spaced apart electrically conductive strips, insulated from said substrate, said spacers substantially parallel to one another in a second direction, substantially perpendicular to said first direction;

each of said strips crossing an alternate isolation region and an active region, and being electrically connected stack gates for memory cells in said active region;

each of said strips positioned over and insulated from a plurality of insulated floating gates, each of which is over an active region;

a plurality of spaced apart first electrical conductors substantially parallel to one another in said second direction, said first conductor forming an electrical contact with a plurality of spaced apart first terminals of said memory cells, with each first terminal being in an active region;

each of said first electrical conductors being positioned between a pair of adjacent electrically conductive strips; and

a plurality of spaced apart second electrical conductors substantially parallel to one another in said first direction, said second conductor forming an electrical contact with a plurality of spaced apart second terminals of said memory cells, with each second terminal being in an active region in said substrate, but with said second conductor otherwise insulated from said substrate.

6. The memory array of claim 5 wherein each of said plurality of first electrical conductors is continuous in said second direction and connects to an isolation region in said substrate between pairs of adjacent first terminals of said memory cells.

7. The memory array of claim 5 wherein each of said spaced apart second electrical conductors is insulated from said plurality of first electrical conductors, with said plurality of first electrical conductors between said substrate and said plurality of second electrical conductors.

8. The memory array of claim 5 further comprising a plurality of pairs of spaced apart insulating spacers, substantially parallel to one another in the second direction, with each pair adjacent to a first electrical conductor and with each spacer abutting one of said strips.

9. A self-aligned method of forming a semiconductor memory array of split gate floating gate memory cells in a semiconductor substrate, each split gate memory cell having a floating gate, a first terminal, a second terminal with a channel region therebetween, a control gate and a coupling gate, said method comprising the steps of:

a) forming a plurality of spaced apart isolation regions on said substrate, substantially parallel to one another in a first direction with an active region between each pair of adjacent isolation regions, said active region comprising a first layer of insulating material on said semiconductor substrate, and a first layer of polysilicon material on said first layer of insulating material;

b) forming a plurality of spaced apart masking regions of a masking material, substantially parallel to one another in a second direction on said active regions and isolation regions, said second direction substantially perpendicular to said first direction;

c) depositing a second layer of insulating material on said masking material, and on said isolation regions and active regions;

d) depositing a second layer of polysilicon material on said second layer of insulating material;

e) anisotropically etching said second layer of polysilicon material until said second layer of polysilicon material partially fills regions between pairs of adjacent spaced apart masking regions;

f) forming a plurality of spaced apart first spacers of an insulating material, substantially parallel to one another in said second direction, each first spacer on said second layer of polysilicon material, and adjacent and contiguous to one of said masking regions with a first region between each pair of adjacent first spacers, each first spacer crossing a plurality of alternating active region and isolation region;

g) etching between pairs of adjacent first spacers in said first region at least through said second layer of polysilicon material, forming a plurality of substantially parallel troughs in said second direction, wherein said second polysilicon material being a connected coupling gate to each of said memory cells in said second direction;

h) forming the first terminal in said substrate in each of said active regions between pairs of adjacent first spacers in said first region through said troughs;

i) forming a conductor in said second direction between each pairs of spaced apart first spacers electrically connected to the first terminal in said substrate;

j) removing said masking material resulting in a plurality of structures, substantially parallel to one another in the second direction;

k) forming an insulating film about each of said structures;

l) forming a plurality of spaced apart second spacers of a polysilicon material, substantially parallel to one another in said second direction each second spacer adjacent and contiguous to one of said structures, with a second region between each pair of adjacent second spacers, each second spacer crossing a plurality of alternating active region and isolation region, each of said second spacers being electrically connected control gates for memory cells in said second direction;

m) etching between pairs of adjacent second spacers in said second region;

n) forming the second terminal in said substrate in each of said active regions between pairs of adjacent second spacers in said second region; and

o) forming a conductor in a first direction, substantially parallel to an active region, electrically connected to the second terminal in said substrate.

10. The method of claim 9 further comprising the step of etching along said second direction under said masking material, after step b).

11. A semiconductor memory array of floating gate split gate memory cells in a semiconductor substrate, each split gate memory cell having a floating gate, a first terminal, a second terminal with a channel region therebetween, a coupling gate and a control gate, said array comprising:

a semiconductor substrate having a plurality of spaced apart active regions substantially parallel to one another in a first direction;

with an isolation region between each pair of active regions;

a plurality of spaced apart spacers of an electrically conductive material, insulated from said substrate, said spacers substantially parallel to one another in a second direction, substantially perpendicular to said first direction;

each of said spacers crossing an alternate isolation region and an active region, and being electrically connected control gates for memory cells in said active region;

a plurality of spaced apart first electrical conductors substantially parallel to one another in said second direction, said first conductor forming an electrical contact with a plurality of spaced apart first terminals of said memory cells, with each first terminal being in an active region;

a plurality of pairs of spaced apart insulating spacers, substantially parallel to one another in the second direction, with each pair adjacent to one of said first electrical conductors;

a plurality of pairs of spaced apart second electrical conductors substantially parallel to one another in said second direction, said second conductor being electrically connected coupling gates for memory cells in said active regions;

each of said second conductors being between an insulating spacer and the substrate, with said second electrical conductor insulated from said substrate and in coupling relationship with a floating gate; and

a plurality of spaced apart third electrical conductors substantially parallel to one another in said first direction, said third conductor forming an electrical contact with a plurality of spaced apart second terminals of said memory cells, with each second terminal being in an active region in said substrate, but with said third conductor otherwise insulated from said substrate.

12. The memory array of claim 11 wherein each of said second conductors is between an insulating spacer and a floating gate.

13. The memory cell array of claim 12 wherein each of said second conductors is electrically connected to an adjacent first electrical conductor.

14. The memory cell array of claim 12 wherein each of said second conductor is insulated from an adjacent first electrical conductor.

15. The memory array of claim 12 wherein each of said plurality of first electrical conductors is continuous in said second direction and connects to an isolation region in said substrate between pairs of adjacent first terminals of said memory cells.

16. The memory array of claim 11 wherein each of said spaced apart third electrical conductors is insulated from said plurality of first and second electrical conductors, with said plurality of first and second electrical conductors between said substrate and said plurality of third electrical conductors.

17. The memory array of claim 11 wherein said plurality of spaced apart spacers are formed in pairs, with one of said first electrical conductors being between two adjacent pairs of said spacers, and with each of said third electrical conductors forming an electrical contact with said substrate between each pair of said spacers.

18. A semiconductor device in a semiconductor substrate, having an array of substantially identical non-volatile memory cells of the stacked gate type, with each memory cell having a first terminal and a second terminal in an active region, said array comprising:

a plurality of contiguous alternating strips of isolation region and active region in said semiconductor substrate, parallel to one another in a first direction;

a plurality of spaced apart first conductive strips, parallel to one another, in a second direction, substantially perpendicular to said first direction, each of said first conductive strips contacting a first terminal in an active region; and

a plurality of spaced apart second conductive strips, parallel to one another, in said first direction, insulated from said plurality of first conductive strips, each of said second conductive strips substantially parallel to a strip of active region and contacting a second terminal in said active region.

19. The array of claim 18 wherein each of said first conductive strips contacts said semiconductor substrate across a plurality of active regions and a plurality of isolation regions in said second direction.

20. The array of claim 18 wherein each of said first conductive strips is a spacer adjacent to an insulator.

21. The array of claim 18 wherein each of said first conductive strips contacts a first region of two adjacent memory cells in an active region.

22. The array of claim 18 wherein each of said second conductive strips contacts a second region of two adjacent memory cells in an active region.

23. A semiconductor device in a semiconductor substrate, having an array of substantially identical non-volatile memory cells of the split gate type with a coupling gate, with each memory cell having a first terminal and a second terminal in an active region, said array comprising:

a plurality of contiguous alternating strips of isolation region and active region in said semiconductor substrate, parallel to one another in a first direction;

a plurality of spaced apart first conductive strips, parallel to one another, in a second direction, substantially perpendicular to said first direction, each of said first conductive strips contacting a first terminal in an active region; and

a plurality of spaced apart second conductive strips, parallel to one another, in said first direction, insulated from said plurality of first conductive strips, each of said second conductive strips substantially parallel to a strip of active region and contacting a second terminal in said active region.

24. The array of claim 23 wherein each of said first conductive strips contacts said semiconductor substrate across a plurality of active regions and a plurality of isolation regions in said second direction.

25. The array of claim 23 wherein each of said first conductive strips is a spacer adjacent to an insulator.

26. The array of claim 23 wherein each of said first conductive strips contacts a first region of two adjacent memory cells in an active region.

27. The array of claim 23 wherein each of said second conductive strips contacts a second region of two adjacent memory cells in an active region.

28. A self aligned method of forming a plurality of row lines and column lines to connect a plurality of semiconductor elements arranged in an array of rows and columns, said method comprising:

forming a structure comprising a plurality of rows of said semiconductor elements on a semiconductor substrate, each row spaced apart from one another with a trench therebetween;

each row of said semiconductor elements having a vertical edge facing said trench;

depositing a first conductive material on said structure, including in said trench and insulated from said substrate;

etching said first conductive material until a recess is formed in said trench, thereby forming a plurality of spaced apart rows of said first conductive material;

depositing a first insulating material on the structure formed after the etching step;

etching said first insulating material until two spaced apart spacers, with a first region therebetween, are formed in said trench, said spacers being arranged in spaced apart rows, adjacent to and contiguous with the vertical edges of said rows of semiconductor elements;

etching said first conductive material in said first region to said substrate, thereby forming two parallel row lines, one adjacent to each row of semiconductor elements;

forming a terminal in said substrate between said row lines in said trench;

forming an insulation about said row lines; and

forming spaced apart column lines, perpendicular to said row lines, connecting to the terminal in said substrate between said row lines.

29. The method of claim 28 further comprising the step of metallizing the first conductive material, prior to the deposition of the first insulating material thereon.

30. The method of claim 28 wherein said spacers insulate said row lines from said column line.

31. A method of forming a plurality of row lines and column lines to connect a plurality of semiconductor elements arranged in an array of rows and columns, said method comprising:

forming a structure comprising a plurality of rows of said semiconductor elements on a semiconductor substrate, each row spaced apart from one another with a trench therebetween;

each row of said semiconductor elements having a vertical edge facing said trench;

depositing a first conductive material on said structure, including in said trench and insulated from said substrate;

etching said first conductive material until a recess is formed in said trench, thereby forming a plurality of spaced apart rows of said first conductive material;

depositing a first insulating material on the structure formed after the etching step;

etching said first insulating material until two spaced apart spacers, with a first region therebetween, are formed in said trench, said spacers being arranged in spaced apart rows, adjacent to and contiguous with the vertical edges of said rows of semiconductor elements;

etching said first conductive material in said first region to said substrate, thereby forming two parallel row lines, one adjacent to each row of semiconductor elements;

forming a terminal in said substrate between said row lines in said trench;

depositing a second insulating material on said spacers and said terminal;

opening a hole in said second insulating material to said second terminal; and

forming spaced apart column lines, perpendicular to said row lines, connecting to the terminal in said substrate between said row lines.

32. The method of claim 31 further comprising the step of metallizing the first conductive material, prior to the deposition of the first insulating material thereon.

33. The method of claim 31 wherein said spacers insulate said row lines from said column line.

34. A method of forming a plurality of row lines and column lines to connect a plurality of semiconductor elements arranged in an array of rows and columns, said method comprising:

forming a structure comprising a plurality of rows of said semiconductor elements on a semiconductor substrate, each row spaced apart from one another with a trench therebetween;

each row of said semiconductor elements having a row line contained therein and having a vertical edge facing said trench;

depositing a first insulating material on said structure, including in said trench;

etching said first insulating material until two spaced apart spacers, with a first region therebetween, are formed in said trench, said spacers being arranged in spaced apart rows, adjacent to and contiguous with the vertical edges of said rows of semiconductor elements;

forming a terminal in said substrate between said row lines in said trench; and

forming spaced apart column lines, perpendicular to said spacers, connecting to the terminal in said substrate between said spacers.