A TEST BOARD FOR TESTING A SEMICONDUCTOR DEVICE UTILIZING FIRST AND SECOND DELAY ELEMENTS IN A SIGNAL-TRANSMISSION-PATH

• US 20020011865A1
• Filed: 09/03/1998
• Published: 01/31/2002
• Est. Priority Date: 05/07/1998
• Status: Active Grant

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: UEDA, MASAHIRO, DEGUCHI, YOSHINORI, TAKAGI, RYOICHI
• Granted Patent: US 6,356,096 B2
• Time in Patent Office: Days
• US Class Current: 324/765
• CPC Class Codes: G01R 31/31937 Timing aspects, e.g. measuring propagation delay G01R31/3191 and G01R31/31922 take precedence; marginal testing G06F11/24

Abstract

A clock CLK is applied to one input of an MUX 3, while data DATA1 is applied to a delay circuit 2 and to one input of a receiver 6. The delay circuit 2 delays the data DATA1 for a predetermined period of time, and outputs a delay data DDT to the other input of the MUX 3. A test-mode signal STM is applied to a control input of the MUX 3. The MUX 3 is then outputs either the clock CLK or the delay data DDT to respective control inputs of the receiver 6 and a drive 8 on the basis of the test-mode signal STM. The receiver 6 compares the data DATA1 and a reference voltage VREF, and performs buffering on the basis of its comparison result to output an internal signal. Thus, a semiconductor device and a test (DUT) board thereof can achieve a high-precision timing test, irrespective of the timing skew of a tester.

Claims

1. A semiconductor device comprising a first input/output buffer cell receiving first and second input signals and a first test-mode signal and buffering said first input signal to output an internal signal,

said first input/output buffer cell comprising:

delay means for receiving said first input signal and delaying said first input signal for a predetermined delay time to output a first delay input signal;

first input-signal selecting means for outputting either of said first delay input signal and said second input signal as a first selection signal on the basis of said first test-mode signal; and

internal-signal output means for buffering said first input signal to output said internal signal, the operation of said internal-signal output means controlled by said first selection signal.

2. The semiconductor device according to claim 1, further comprising:

a second input/output buffer cell for buffering said internal signal to output an output signal to the outside, the operation of said second input/output buffer cell controlled by said second input signal.

3. The semiconductor device according to claim 2, further comprising:

an internal-signal processing circuit for processing said internal signal in a predetermined way to output a processed signal; and

signal control means for receiving a second test-mode signal and controlling the validity or invalidity of outputting said processed signal to said first and said second input/output buffer cells on the basis of said second test-mode signal.

4. The semiconductor device according to claim 1, further comprising:

an internal-signal processing circuit for processing said internal signal in a predetermined way to output a processed signal;

second input-signal selecting means for receiving a second test-mode signal and outputting either of said processed signal and said internal signal as a second selection signal on the basis of said second test-mode signal; and

a second input/output buffer cell for buffering said second selection signal to output an output signal to the outside, the operation of said second input/output buffer cell controlled by said second input signal.

5. The semiconductor device according to claim 1, wherein

said delay means comprises:

an inverter chain comprising a plurality of series-connected inverters with its first-stage inverter receiving said first input signal at its input;

inverter delay-time control means for controlling respective signal propagation delay times of said plurality of inverters; and

a selector for selectively outputting a signal related to one of the outputs of said plurality of inverters as said first delay input signal.

6. The semiconductor device according to claim 5, wherein

said plurality of inverters includes an odd number, not less than three, of inverters in loop connection with the output of its last-stage inverter connected to the input of its first-stage inverter;

and

said inverter delay-time control means includes;

signal comparison means for comparing the number of reference oscillations and the number of oscillations of an oscillating signal obtained by oscillating said odd number of inverters in loop connection during a predetermined period of time, to output its comparison result; and

control-signal output means for determining said signal propagation delay time on the basis of said comparison result, and applying a control signal indicating said signal propagation delay time to said plurality of inverters.

7. The semiconductor device according to claim 5, wherein

a total signal propagation delay time of said plurality of inverters is set to be the same as a cycle of said first input signal.

8. A test board for testing a semiconductor device,

said semiconductor device including at least first and second input terminals and an input/output buffer cell for buffering a signal obtained from said first input terminal to output an internal signal, the operation of said semiconductor device controlled by a signal obtained from said second input terminal,

said test board comprising:

first delay means for delaying a signal to be transmitted therethrough for a first signal propagation delay time;

second delay means for delaying a signal to be transmitted therethrough for a second signal propagation delay time different from said first signal propagation delay time; and

signal-transmission-path forming means for receiving a first test signal and forming, in a first test mode, a first signal transmission path along which said first test signal is transmitted through said first delay means to said first input terminal of said semiconductor device, and a second transmission path along which said first test signal is transmitted through said second delay means to said second input terminal of said semiconductor device.

9. The test board according to claim 8, wherein

said second signal propagation delay time is set longer than said first signal propagation delay time;

said test board further comprising;

third delay means for delaying a signal to be transmitted therethrough for a third signal propagation delay time; and

fourth delay means for delaying a signal to be transmitted therethrough for a fourth signal propagation delay time shorter than said third signal propagation delay time,

in a second test mode, said signal-transmission-path forming means further receiving a second test signal and forming a third signal transmission path along which said second test signal is transmitted through said third delay means to said first input terminal of said semiconductor device, and a fourth signal transmission path along which said second test signal is transmitted through said fourth delay means to said second input terminal of said semiconductor device.

10. The test board according to claim 8, wherein

said semiconductor device further includes an output terminal capable of outputting a signal obtained from said first input terminal at a setting of a predetermined condition, without logically processing said signal,

said test board further comprising:

third delay means for delaying a signal to be transmitted therethrough for a third signal propagation delay time;

fourth delay means for delaying a signal to be transmitted therethrough for a fourth signal propagation delay time equal to said third signal propagation delay time; and

tolerable-output-time delay means for delaying a signal to be transmitted therethrough for a predetermined tolerable output time,

said signal-transmission-path forming means further receiving a second test signal,

in a first mode for testing an output time, said signal-transmission-path forming means forming a first signal transmission path for testing an output time, capable of outputting a signal obtained by transmitting said second test signal through said fourth delay means and said tolerable-output-time delay means, to the outside as a first comparison signal,

in a second mode for testing an output time, said signal-transmission-path forming means forming second and third signal propagation paths for testing an output time, along which said first and said second test signals are transmitted through said third and said fourth delay means to said first and said second input terminals, respectively, and a fourth signal transmission path for testing an output time, capable of outputting a signal obtained from said output terminal to the outside as a second comparison signal.

11. The test board according to claim 8, wherein

said signal-propagation-path forming means, in said first test mode, terminates said first and said second input terminals via first and second terminating resistors, respectively.

12. The test board according to claim 8, wherein

said second input terminal includes first and second differential input terminals;

the operation of said semiconductor device is controlled by a signal obtained from said first and said second differential input terminals; and

said signal-transmission-path forming means, in said first test mode, applies said first test signal through said second delay means to said first differential input terminal of said second input terminal of said semiconductor device, and applies a fixed voltage to said second differential input terminal.

13. The test board according to claim 12, wherein

said signal-transmission-path forming means, in said first test mode, terminates said first input terminal via a first terminating resistor, and connects said first and said second differential input terminals with a resistance element.

14. The test board according to claim 8, wherein

said first and said second signal transmission paths are formed in such a manner that a transmission path of said first test signal branches into two with a magnetic relay, an MOS transistor, or a power splitter.

15. The test board according to claim 8, wherein

said first and said second delay means are formed of an axial cable determining a delay time according to its length, or an active delay element capable of setting a delay time through a predetermined setting operation.