SEMICONDUCTOR DEVICE WITH A THIN GATE STACK HAVING A PLURALITY OF INSULATING LAYERS

• US 20020014657A1
• Filed: 03/03/1998
• Published: 02/07/2002
• Est. Priority Date: 03/03/1998
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc., Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: International Business Machines Corporation
• Inventors: OKUMURA, KATSUYA, OHIWA, TOKUHISA, GAMBINO, JEFFREY, SHIOZAWA, JUN-ICHI
• Granted Patent: US 6,369,423 B2
• Time in Patent Office: Days
• US Class Current: 257/327
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H10B 12/05 Making the transistor
• CPC Class Codes: H10B 12/485 Bit line contacts

Abstract

The present invention intends to provide a semiconductor device capable of realizing a thin gate stack and the manufacturing method thereof. A gate cap layer and/or a protection insulating film (an etching stopper) has a plurality of insulating materials such as oxide and nitride stacked on each other. With this structure, an insulating layer having an etching rate lower than that of the interlayer insulating layer, for example, can be exposed during the etching of the interlayer insulating layer, and the gate stack can be formed thin and the aspect ratio of the contact hole formed in the device can be reduced. The present invention can realize a thin gate stack in such a manner, and thus is suitable for a SAC used in a DRAM.

Claims

1. A semiconductor device comprising:

a substrate;

a gate oxide film formed selectively on the substrate;

a gate electrode formed on the gate oxide film;

a gate cap layer formed on the gate electrode;

a protection insulating film formed on the gate cap layer and sidewalls of the gate electrode, the protection insulating film comprising a plurality of insulating films; and

a diffusion layer formed on a surface of the substrate so as to contact with a channel forming region formed below the gate electrode.

2. A semiconductor device according to claim 1, wherein the protection insulating film has a nitride layer formed on the gate cap layer and a silicon layer formed on the nitride layer.

3. A semiconductor device comprising

a substrate;

a gate oxide film formed selectively on the substrate;

a gate electrode formed on the gate oxide film;

a gate cap layer formed on the gate electrode, the gate cap layer including a plurality of insulating layers;

a protection insulating film formed on the gate cap layer and the sidewalls of the gate electrode; and

a diffusion layer formed on a surface of the substrate so as to contact with a channel forming region formed below the gate electrode.

4. A semiconductor device according to claim 3, wherein the gate cap layer has a nitride layer formed on the gate electrode and an oxide layer formed on the nitride layer.

5. A semiconductor device comprising:

a substrate;

a gate oxide film formed selectively on the substrate;

a gate electrode formed on the gate oxide film;

a gate cap layer formed on the gate electrode, the gate cap layer including a plurality of insulating layers;

a protection insulating film formed on the gate cap layer and sidewalls of the gate electrode, the protection insulating film including a plurality of insulating layers; and

a diffusion layer formed on a surface of the substrate so as to contact with a channel forming region formed below the gate electrode.

6. A semiconductor device according to claim 5, wherein the protection insulating film has a nitride layer formed on the gate cap layer and a silicon layer formed on the nitride layer, and the gate cap layer has a nitride layer formed on the gate electrode and an oxide layer formed on the nitride layer.

7. A manufacturing method of a semiconductor device, comprising the steps of:

forming a gate electrode on a gate oxide film formed on a substrate;

forming a gate cap layer on the gate electrode;

forming a diffusion layer on a surface of the substrate with use of the gate cap layer as a mask;

forming a protection insulating film including a plurality of insulating films on the substrate so as to cover the gate cap layer and the gate electrode;

forming an interlayer insulating layer on the protection insulating film;

etching the interlayer insulating layer and the protection insulating film so as to form an opening at the gate electrode in a self-aligned manner, thereby to expose the surface of the substrate at a bottom of the opening; and

forming a wiring layer connected to the exposed surface of the substrate.

8. A manufacturing method of a semiconductor device according to claim 7, wherein the protection insulating film has a nitride layer formed on the substrate and a silicon layer formed on the nitride layer.

9. A manufacturing method of a semiconductor device, comprising the steps of:

forming a gate electrode on a gate oxide film formed on a substrate;

forming a gate cap layer including a plurality of insulating layers on the gate electrode;

forming a diffusion layer on a surface of the substrate with use of the gate cap layer as a mask;

forming a protection insulating film on the substrate so as to cover the gate cap layer and the gate electrode;

forming an interlayer insulating layer on the protection insulating film;

etching the interlayer insulating layer and the protection insulating film to form an opening at the gate electrode in a self-aligned manner, thereby to expose the surface of the substrate at a bottom of the opening; and

forming a wiring layer connected to the exposed surface of the substrate.

10. A manufacturing method of a semiconductor device according to claim 9, wherein the gate cap layer has a nitride layer formed on the gate electrode and an oxide layer formed on the nitride layer.

11. A manufacturing method of a semiconductor device, comprising the steps of:

forming a gate electrode on a gate oxide film formed on a substrate;

forming a gate cap layer including a plurality of insulating layers on the gate electrode;

forming a diffusion layer on a surface of the substrate with use of the gate cap layer as a mask;

forming a protection insulating film including a plurality of insulating films on the substrate so as to cover the gate cap layer and the gate electrode;

forming an interlayer insulating layer on the protection insulating film;

etching the interlayer insulating layer and the protection insulating film to form an opening at the gate electrode in a self-aligned manner, thereby to expose the surface of the substrate at a bottom of the opening; and

forming a wiring layer connected to the exposed surface of the substrate.

12. A manufacturing method of a semiconductor device according to claim 11, wherein the protection insulating film has a nitride layer formed on the gate cap layer and a silicon layer formed on the nitride layer, and the gate cap layer has a nitride layer formed on the gate electrode and an oxide layer formed on the nitride layer.