Method of making wireless semiconductor device, and leadframe used therefor

• US 20020014704A1
• Filed: 07/31/2001
• Published: 02/07/2002
• Est. Priority Date: 07/31/2000
• Status: Active Grant

• Current Assignee: ROHM Co., Ltd.
• Original Assignee: ROHM Co., Ltd.
• Inventors: Horie, Yoshitaka
• Granted Patent: US 6,897,567 B2
• Time in Patent Office: Days
• US Class Current: 257/779
• CPC Class Codes: H01L 2224/16245 the item being metallic
• CPC Class Codes: H01L 2224/291 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/29111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/2919 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/32014 the layer connector being smaller than the bonding area, e.g. bond pad
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/37099 Material
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2224/83 using a layer connector
• CPC Class Codes: H01L 2224/8319 Arrangement of the layer connectors prior to mounting
• CPC Class Codes: H01L 2224/83801 Soldering or alloying
• CPC Class Codes: H01L 2224/84801 Soldering or alloying
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/3107 the device being completely enclosed
• CPC Class Codes: H01L 23/49551 characterised by bent parts
• CPC Class Codes: H01L 24/33 of a plurality of layer connectors
• CPC Class Codes: H01L 24/40 of an individual strap connector
• CPC Class Codes: H01L 24/83 using a layer connector
• CPC Class Codes: H01L 24/84 using a strap connector
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01011 : Sodium [Na]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01051 : Antimony [Sb]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/0132 : Binary Alloys
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/0665 : Epoxy resin
• CPC Class Codes: H01L 2924/15747 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19043 : being a resistor

Abstract

A method of making a semiconductor device is provided. The method includes the following steps. First, a semiconductor chip is mounted on a lower conductor, with first solder material applied between the chip and the lower conductor. Then, an upper conductor is placed on the chip, with second solder material applied between the chip and the upper conductor. Then, the first and the second solder materials are heated up beyond their respective melting points. Finally, the first and the second solder materials are allowed to cool down, so that the first solder material solidifies earlier than the second solder material.

Claims

1. A method of making a semiconductor device, the method comprising the steps of:

mounting a semiconductor chip on a lower conductor, with first solder material applied between the chip and the lower conductor;

positioning an upper conductor on the chip, with second solder material applied between the chip and the upper conductor;

heating up the first and the second solder materials beyond melting points of the respective materials; and

solidifying the first and the second solder materials;

wherein the first solder material is caused to solidify earlier than the second solder material.

2. The method according to claim 1, wherein the melting point of the first solder material is higher than the melting point of the second solder material.

3. The method according to claim 1, wherein the heating of the first solder material is terminated earlier than the heating of the second solder material.

4. The method according to claim 1, wherein the heating of the first and the second solder materials is performed by contacting the lower and the upper conductors with first and second heaters, respectively.

5. The method according to claim 1, wherein the semiconductor chip includes a flat lower electrode and a protruding upper electrode, the lower electrode being connected to the lower conductor, the upper electrode being connected to the upper conductor.

6. The method according to claim 1, further comprising the step of preparing a conductive frame which includes the lower and the upper conductors.

7. The method according to claim 6, wherein the lower conductor comprises a die pad portion and lower lead portions extending from the die pad portion, the semiconductor chip being mounted on the die pad portion.

8. The method according to claim 7, wherein the upper conductor comprises upper lead portions divided into first and second groups.

9. The method according to claim 8, further comprising the step of removing at least one of the lower and the upper lead portions from the frame.

10. The method according to claim 8, wherein the frame comprises first and second common bars parallel to each other, the upper lead portions in the first group extending from the first common bar toward the second common bar, the upper lead portions in the second group extending from the second common bar toward the first common bar.

11. The method according to claim 6, further comprising the step of rotating the upper conductor about an axis relative to the lower conductor, so that the upper conductor comes into facing relation to the lower conductor.

13. The frame according to claim 12, wherein the lower and the upper lead portions are elongated in a common direction.

14. The frame according to claim 12, wherein the lower and upper lead portions are elongated along said axis, the first and the second common bars being perpendicular to said axis.

16. The device according to claim 15, wherein the first electrode is flat, the second electrode being unflat, the second solder material having a lower melting point than the first solder material.

12. A conductive frame used for making a semiconductor device, the frame comprising:

a lower conductive pattern which includes a die pad portion and lower lead portions extending from the die pad portion;

an upper conductive pattern which includes first and second common bars parallel to each other, and upper lead portions divided into first and second groups, the upper lead portions in the first group extending from the first common bar toward the second common bar, the upper lead portions in the second group extending from the second common bar toward the first common bar;

wherein the lower and the upper conductive patterns are rotatable about an axis relative to each other, so that they come into facing relation.

15. A semiconductor device comprising:

a semiconductor chip having a first surface and a second surface opposite to the first surface;

a first electrode provided at the first surface;

a second electrode provided at the second surface;

a first lead connected to the first electrode by first solder material; and

a second lead connected to the second electrode by second solder material;

wherein the first solder material differs in melting point from the second solder material.