Face to face chip

• US 20020016021A1
• Filed: 10/02/2001
• Published: 02/07/2002
• Est. Priority Date: 10/14/1999
• Status: Active Grant

• Current Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Sutherland, Ivan E.
• Granted Patent: US 6,500,696 B2
• Time in Patent Office: Days
• US Class Current: 438/107
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06531 Non-galvanic coupling, e.g. capacitive coupling
• CPC Class Codes: H01L 23/48 Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
• CPC Class Codes: H01L 23/642 Capacitive arrangements H01L23/49589, H01L23/645, H01L23/647, H01L23/66 take precedence; capacitive effects between wiring layers on the semiconductor body H01L23/5222
• CPC Class Codes: H01L 25/0652 the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 2924/01046 Palladium [Pd]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/3025 Electromagnetic shielding

Abstract

An integrated circuit device includes first and second arrays of semiconductor dice. Each array of dice is arranged in face-to-face relation to the other array of dice, thus forming a lower layer of dice and an upper layer of dice. The layers are aligned so that each upper layer die straddles two or more of the lower layer dice, thus defining overlap regions. In the overlap regions, signal pads of one layer are aligned with corresponding signal pads of the other layer. The two layers are spaced apart, thus creating a capacitance-based communication path between the upper and lower layers via the signal paths.

Claims

1. An integrated circuit device comprising:

a first semiconductor die having first signal pads formed on a major surface thereof;

a second semiconductor die having second signal pads formed on a major surface thereof; and

said first die arranged in face-to-face manner with said second die so that at least some of said first signal pads are capacitively coupled to at least some of said second signal pads.

2. The integrated circuit device of claim 1 further including a non-conductive dielectric material disposed between said first and second dice.

3. The integrated circuit device of claim 1 wherein said major surface of said first die includes a non-conductive dielectric material disposed thereupon.

4. The integrated circuit device of claim 1 wherein said major surfaces of said first and second dice have raised areas, a raised area on one die contacting an area on the other die that is absent signal pads so that said dice are spaced apart from each other.

5. The integrated circuit device of claim 1 wherein said first die includes recesses disposed in said major surface, said at least some of said first signal pads being disposed in said recesses.

6. The integrated circuit device of claim 1 further including a third semiconductor die having third signal pads formed on a major surface thereof;

said first die arranged in face-to-face manner with and spaced apart from said third die;

said first die overlapping both said second and third dice;

said first die aligned relative to said second and third dice so that said first signal pads are aligned with some of said second and third signal pads.

7. The integrated circuit device of claim 6 wherein said signal pads of said first, second, and third dice are arranged along peripheries of the respective major surfaces thereof.

8. The integrated circuit device of claim 6 wherein said first, second, and third dice have a rectangular shape.

9. The integrated circuit device of claim 1 wherein said first and second dice have an octagonal shape.

10. An integrated circuit device comprising:

a first plurality of dice arranged in a first planar array;

a first set of signal pads disposed on surfaces of the first plurality of dice;

a second plurality of dice arranged in a second planar array;

a second set of signal pads disposed on surfaces of the second plurality of dice;

wherein the first plurality of dice and the second plurality of dice are positioned within the integrated circuit device such that each die of the first plurality of dice partially overlie at least two dice of the second plurality of dice, thereby defining areas of overlap; and

wherein the first plurality of dice and the second plurality of dice are positioned within the integrated circuit device such that at least some of the first set of signal pads are capacitively coupled to corresponding signal pads of the second set of signal pads.

11. The integrated circuit device of claim 10 wherein said first plurality of dice are spaced apart from said second plurality of dice by an amount sufficient to provide capacitance between some signal pads of said first plurality of dice and some signal pads of said second plurality of dice in said areas of overlap.

12. The integrated circuit device of claim 11 wherein each of said first plurality of dice is spaced apart from said second plurality of dice by a dielectric material.

13. The integrated circuit device of claim 11 wherein said first plurality of dice and said second plurality of dice have major surfaces upon which are disposed said signal pads, some portions of said major surfaces being raised relative to other portions of said major surfaces, thereby spacing apart said first plurality of dice from said second plurality of dice.

14. The integrated circuit device of claim 11 wherein said first plurality of dice and said second plurality of dice have major surfaces upon which are disposed said signal pads, some of said signal pads being recessed relative to their respective major surfaces so signal pads on said first plurality of dice are spaced apart from signal pads on said second plurality of dice.

15. The integrated circuit device of claim 10 wherein said first plurality of dice have a square shape.

16. The integrated circuit device of claim 15 wherein said second plurality of dice have a square shape, said first plurality of dice and said second plurality of dice being arranged in a repeating pattern.

17. The integrated circuit device of claim 15 wherein said second plurality of dice have a rectangular shape, said first plurality of dice and second dice being arranged in a repeating pattern.

18. The integrated circuit device of claim 10 wherein said first plurality of dice and second plurality of dice have a rectangular shape, said first plurality of dice and said second plurality of dice being arranged in a repeating pattern.

20. The method of claim 19 wherein said steps of providing first dice and second dice include a step of forming a dielectric layer on some of said first dice and second dice, so that signal pads in said overlap areas are spaced apart.

21. The method of claim 19 wherein said first polygonal shape is a rectangle.

22. The method of claim 21 wherein said second polygonal shape is a rectangle.

23. The method of claim 21 wherein said second polygonal shape is a square.

24. The method of claim 19 wherein said first and second polygonal shapes each is an octagon.

19. A method of fabricating an integrated circuit device, comprising:

providing a plurality of first dice, said dice each having a first polygonal shape and having signal pads formed on a surface thereof;

providing a plurality of second dice, said dice each having a second polygonal shape and having signal pads formed on a surface thereof;

arranging said first dice to form a first repeating pattern;

arranging said second dice to form a second repeating pattern;

further arranging said first dice so that signal pads thereof are in face-to-face relation with signal pads of said second dice;

aligning said first dice so that each first die overlaps at least two of said second dice, thereby defining overlap areas;

further aligning said first dice so that signal pads thereof located in said overlap areas coincide with some signal pads of said second dice;

capacitively coupling some signal pads of said first dice to some signal pads of said second dice in said overlap areas, thereby providing a signal path between said plurality of first and second dice.