Method for sorting integrated circuit devices

• US 20020017482A1
• Filed: 08/28/2001
• Published: 02/14/2002
• Est. Priority Date: 01/17/1997
• Status: Active Grant

• Current Assignee: Reymond J. Beffa
• Original Assignee: Reymond J. Beffa
• Inventors: Beffa, Reymond J.
• Granted Patent: US 6,504,123 B2
• Time in Patent Office: Days
• US Class Current: 209/573
• CPC Class Codes: B07C 5/3412 according to a code applied to the object which indicates a property of the object, e.g. quality class, contents or incorrect indication sorting according to size measured by light-responsive means B07C5/10; sorting according to optical properties B07C5/342; for packages B65D79/02; for information carriers G06K7/00
• CPC Class Codes: B07C 5/344 according to electric or electromagnetic properties sorting according to size measured electrically or electronically B07C5/08; material testing by magnetic means G01N24/00, G01N27/00, by electrical means G01N27/00; electrical measuring devices in general G01R; coin testing G07D5/00
• CPC Class Codes: G01R 31/2851 Testing of integrated circuits [IC] G01R31/317 takes precedence; testing individual devices G01R31/26; testing printed circuits G01R31/2801
• CPC Class Codes: H01L 2223/5444 for electrical read out
• CPC Class Codes: H01L 2223/54473 for use after dicing
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method for sorting integrated circuit (IC) devices of the type having a substantially unique identification (ID) code, such as a fuse ID, includes automatically reading the ID code of each of the IC devices and sorting the IC devices in accordance with their automatically read ID codes.

Claims

1. An integrated circuit manufacturing process for separating integrated circuit devices for enhanced reliability testing from a group of integrated circuit devices, said integrated circuit devices each having a substantially unique identification code, the process comprising:

storing a flag in connection with the identification code of each integrated circuit device of the integrated circuit devices in a group indicating if each integrated circuit device needs enhanced reliability testing;

reading the identification code of each integrated circuit device of the integrated circuit devices in the group;

accessing the enhanced reliability testing flag stored in connection with each of the identification codes for each integrated circuit device in the group;

sorting the integrated circuit devices in the group from their enhanced reliability testing flag; and

performing enhanced reliability testing on integrated circuit devices needing enhanced reliability testing.

2. The method of claim 1, wherein the step of sorting the integrated circuit devices comprises sorting the integrated circuit devices in accordance with their enhanced reliability testing flag indicates they come from one of a reliable semiconductor wafer and an unreliable semiconductor wafer.