Trench structure substantially filled with high-conductivity material

• US 20020024091A1
• Filed: 06/11/2001
• Published: 02/28/2002
• Est. Priority Date: 06/30/1999
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Brian S. Mo
• Inventors: Mo, Brian S.
• Granted Patent: US 6,737,323 B2
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 21/28061 the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction H01L21/28052 takes precedence
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A trench structure that is substantially filled with high-conductivity material such as refractory metal particularly suitable for fast switching trench MOSFET applications. The trench is first lined by a dielectric material such as silicon dioxide. A layer of polysilicon is then formed on the dielectric material and provides buffering for stress relief. The trench is then filled substantially with refractory metal such as tungsten.

Claims

1. A trench structure comprising:

a trench formed in a substrate;

a dielectric material lining at least a wall of the trench to form a dielectric layer;

a buffer layer formed on the dielectric layer, the buffer layer having a first conductivity; and

a high-conductivity layer formed adjacent to and electrically coupled to the buffer layer, the high-conductivity layer having a second conductivity greater than the first conductivity.

2. The trench structure of claim 1 wherein the buffer layer comprises polysilicon.

3. The trench structure of claim 2 wherein the polysilicon is at least 2,000 to 3,000 Å

in thickness.

4. The trench structure of claim 2 wherein the high-conductivity layer fills a center portion of the trench and comprises metal.

5. The trench structure of claim 4 wherein the high-conductivity layer comprises any one of a number of refractory metals including tungsten, titanium, platinum, or any combination thereof.

6. The trench structure of claim 4 wherein the trench is formed in a silicon substrate and the dielectric material comprises silicon-dioxide.

7. The trench structure of claim 6 wherein the high-conductivity layer comprises tungsten deposited using low-pressure chemical vapor deposition processing, and wherein the trench structure further comprises a layer of polycide between the buffer layer and the high-conductivity layer.

8. The trench structure of claim 7 further comprising a fluorinated interface between the dielectric layer and the wall of the trench.

9. A trench metal-oxide-semiconductor field effect transistor (MOSFET) comprising:

a trench formed in a silicon substrate;

a gate oxide layer lining side-walls and bottom of the trench;

a polysilicon buffer layer lining the gate oxide layer; and

a metal layer filling a center portion of the trench.

10. The trench MOSFET of claim 9 further comprising source regions of a first conductivity type formed on either sides of the trench and inside a body region of a second conductivity type.

11. The trench MOSFET of claim 10 wherein the metal layer comprises tungsten.

12. The trench MOSFET of claim 11 wherein the trench further comprises a layer of polycide sandwiched between the polysilicon buffer layer and the metal layer.

13. The trench MOSFET of claim 12 wherein the tungsten is formed by low pressure chemical vapor deposition processing using hexafluoride as a precursor.

15. The trench transistor of claim 14 wherein the trench further comprises:

a buffer polysilicon layer lining the gate oxide layer; and

a metal layer filling a center portion of the trench.

16. The trench transistor of claim 15 wherein the metal layer comprises tungsten, and wherein a layer of polycide is sandwiched between the metal layer and the buffer polysilicon layer.

18. The method of claim 17 wherein the step of forming a layer of buffer material comprises forming a layer of polysilicon.

19. The method of claim 18 wherein the step of forming a layer of polysilicon further comprises a step of implanting the layer of polysilicon.

20. The method of claim 18 wherein the step of filling a second portion of the trench with a high-conductivity material comprises forming a layer of refractory metal such as tungsten.

21. The method of claim 20 wherein the step of forming a layer of refractory metal comprises a low pressure chemical vapor deposition (LPCVD) process.

22. The method of claim 21 wherein a fluoride-containing precursor is used in the LPCVD process.

23. The method of claim 21 wherein the fluoride-containing precursor comprises tungsten hexafluoride.

24. The method of claim 20 wherein the trench structure is formed as part of a trench transistor, and wherein the steps forming the trench occur after steps involving formation of dopant junctions.

25. The method of claim 24 further comprising a step alloy after the trench structure is formed whereby polycide is formed at an interface between the metal layer and the polysilicon buffer layer.

27. The method of claim 26 wherein the step of filling comprises depositing tungsten by the LPCVD process using tungsten hexafluoride as a precursor.

14. A trench transistor comprising:

a trench extending into a bulk silicon portion of a substrate;

a gate oxide layer lining the trench walls and bottom; and

a fluorinated interface region between the bulk silicon portion of the substrate and the gate oxide layer.

17. A method for fabricating a trench structure in a substrate, the method comprising the steps of:

(a) forming a trench in the substrate;

(b) forming a dielectric layer to line the trench;

(c) forming a layer of buffer material on the dielectric layer to fill a first portion of the trench, the buffer material having a first electrical conductivity; and

(d) filling a second portion of the trench with a high-conductivity material having a second electrical conductivity, the second electrical conductivity being greater than the first electrical conductivity.

26. A method for fabricating a trench transistor, the method comprising:

(a) forming a trench in a bulk silicon region of a substrate;

(b) growing a gate oxide layer to line the trench;

(c) depositing a conformal layer of polysilicon on the gate oxide layer to fill a first portion of the trench; and

(d) substantially filling a remainder of the trench with a metal layer formed in a low pressure chemical vapor deposition (LPCVD) process.