Heat sink with alignment and retaining features

• US 20020024798A1
• Filed: 08/29/2001
• Published: 02/28/2002
• Est. Priority Date: 06/30/1998
• Status: Active Grant

• Current Assignee: David J. Corisis, Larry D. Kinsman, Leonard E. Mess, Walter L. Moden
• Original Assignee: David J. Corisis, Larry D. Kinsman, Leonard E. Mess, Walter L. Moden
• Inventors: Corisis, David J., Kinsman, Larry D., Moden, Walter L., Mess, Leonard E.
• Granted Patent: US 6,525,943 B2
• Time in Patent Office: Days
• US Class Current: 361/719
• CPC Class Codes: H01L 2225/1023 the support being an insulating substrate
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 2225/1082 for improving alignment between containers, e.g. interlocking features
• CPC Class Codes: H01L 2225/1094 Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/3675 characterised by the shape of the housing
• CPC Class Codes: H01L 25/105 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y10T 428/24298 Noncircular aperture [e.g., slit, diamond, rectangular, etc.]

Abstract

An apparatus for providing heat sinks or heat spreaders for stacked semiconductor devices. Alignment apparatus may be included for the alignment of the stacked semiconductor devices. An enclosure may be used as the heat sink or heat spreader.

Claims

1. A semiconductor device assembly comprising:

a first substrate having a first surface, a second surface, and a plurality of circuits located on the first surface and the second surface;

a first semiconductor device located on the first surface of the first substrate, the semiconductor device having a first surface, a second surface, and a periphery, the second surface of the semiconductor device connected to the first surface of the first substrate;

a second substrate having a first surface, a second surface, at least one circuit located on the first surface thereof, at least one aperture therein, and at least one alignment pin having a portion thereof secured in a portion of the at least one aperture;

a first heat transfer device having at least one aperture therein and at least one slot therein, the first heat transfer device in contact with a portion of the first semiconductor device, the at least one alignment pin of the second substrate extending through the at least one aperture in the first heat transfer device; and

at least one connector extending between a circuit on the second surface of the first substrate and a circuit on the first surface of the second substrate.

2. The semiconductor device assembly of claim 1, further comprising:

a third substrate having a first surface, a second surface, a plurality of circuits thereon, at least one circuit located on the first surface and the second surface;

a second semiconductor device located on the first surface of the third substrate; and

at least one connector extending between a circuit on the first surface of the first substrate and a circuit on the second surface of the third substrate, the connector extending through the at least one slot in the first heat transfer device.

3. The semiconductor device assembly of claim 2, further comprising:

a second heat transfer device in contact with the first surface of the second semiconductor device, the second heat transfer device having at least one aperture therein, the at least one alignment pin of the second substrate having a portion thereof extending into the at least one aperture in the second heat transfer device.

4. The semiconductor device assembly of claim 2, further comprising:

a third heat transfer device, the third heat transfer device in contact with a portion of the second surface of the third substrate and a portion of the first surface of the first heat transfer device.

5. The semiconductor device assembly of claim 2, further comprising:

a fourth substrate having a first surface, a second surface, a plurality of circuits thereon, at least one circuit located on the first surface and the second surface;

a third semiconductor device located on the first surface of the fourth substrate;

another first heat transfer device having at least one aperture therein and at least one slot therein, the another first heat transfer device connected to the fourth substrate, the at least one alignment pin of the second substrate extending through the at least one aperture in the another first heat transfer device;

at least one connector extending between a circuit on the first surface of the third substrate and a circuit on the second surface of the fourth substrate, the connector extending through the at least one slot in the another first heat transfer device; and

a fourth heat transfer device located on the at least one alignment pin of the second substrate, the fourth heat transfer device located between the first heat transfer device and the another heat transfer device.

6. The semiconductor device assembly of claim 3, wherein the second heat transfer device includes fins thereon.

7. A semiconductor device assembly comprising:

a first substrate having a first surface, a second surface, a plurality of circuits on at least one of the first surface and the second surface, at least one circuit located on the first surface and the second surface;

a first semiconductor device located on the first surface of the first substrate, the semiconductor device having a first surface, a second surface, and a periphery, the second surface of the semiconductor device connected to the first surface of the first substrate;

a first heat transfer device having at least one aperture therein and at least one slot therein, the first heat transfer device in contact with a portion of the first semiconductor device, said first heat transfer device extending substantially parallel and outwardly beyond a periphery of said first substrate;

at least one connector connected to a circuit on the second surface of the first substrate;

a second substrate having a first surface, a second surface, a plurality of circuits thereon, at least one circuit located on the first surface and the second surface;

a second semiconductor device located on the first surface of the second substrate, the second semiconductor device having a first surface, a second surface, and a periphery, the second surface of the second semiconductor device connected to the first surface of the second substrate; and

at least one first connector extending between a circuit on the first surface of the first substrate and a circuit on the second surface of the second substrate, the at least one connector extending through the at least one slot in the first heat transfer device.

8. The semiconductor device assembly of claim 7, further comprising:

a second heat transfer device having at least one aperture therein and at least one slot therein, the second heat transfer device in contact with a portion of the second semiconductor device.

9. The semiconductor device assembly of claim 7, wherein the first heat transfer device includes at least one T-shaped portion and at least one L-shaped portion.

10. The semiconductor device assembly of claim 9, wherein a portion of the at least one T-shaped portion of the first heat transfer device retains a portion of the first substrate therein.

11. The semiconductor device assembly of claim 10, wherein a portion of the at least one L-shaped portion of the first heat transfer device retains a portion of the first substrate therein.

13. The semiconductor device assembly of claim 12, further comprising:

at least one fin connected to a portion of the enclosure.

15. The semiconductor device assembly of claim 14, further comprising:

a third substrate having a first surface, a second surface, a plurality of circuits thereon, at least one circuit located on the first surface and the second surface;

a second semiconductor device located on the first surface of the third substrate; and

at least one connector extending between a circuit on the first surface of the first substrate and a circuit on the second surface of the third substrate, the at least one connector extending through the at least one slot in the first heat transfer member.

16. The semiconductor device assembly of claim 15, further comprising:

a second heat transfer member in contact with the first surface of the second semiconductor member, the second heat transfer device having at least one aperture therein, the at least one alignment pin of the second substrate having a portion thereof extending into the at least one aperture in the second heat transfer member.

17. The semiconductor device assembly of claim 15, further comprising:

a third heat transfer member, the third heat transfer member in contact with a portion of the second surface of the third substrate and a portion of the first surface of the first heat transfer member.

18. The semiconductor device assembly of claim 15, further comprising:

a fourth substrate having a first surface, a second surface, a plurality of circuits thereon, at least one circuit located on the first surface and the second surface;

a third semiconductor device located on the first surface of the fourth substrate;

another first heat transfer member having at least one aperture therein and at least one slot therein, the another first heat transfer member connected to the fourth substrate, the at least one alignment pin of the second substrate extending through the at least one aperture in the another first heat transfer member;

at least one connector extending between a circuit on the first surface of the third substrate and a circuit on the second surface of the fourth substrate, the at least one connector extending through the at least one slot in the another first heat transfer member; and

a fourth heat transfer member located on the at least one alignment pin of the second substrate, the fourth heat transfer member located between the first heat transfer member and the another heat transfer member.

19. The semiconductor device assembly of claim 16, wherein the second heat transfer member includes fins thereon.

12. A semiconductor device assembly comprising:

a first substrate having a first surface, a second surface, a plurality of circuits located on at least one of the first surface and the second surface, at least two circuits located on the first surface and the second surface;

a first semiconductor device located directly on the first surface of the first substrate, the semiconductor device having a first surface, a second surface, and a periphery, the second surface of the semiconductor device connected to the first surface of the first substrate;

at least one connector connected to a circuit on the second surface of the first substrate;

a second substrate having a first surface, a second surface, a plurality of circuits thereon, at least one circuit located on the first surface and the second surface;

a second semiconductor device located on the first surface of the second substrate, the second semiconductor device having a first surface, a second surface, and a periphery, the second surface of the second semiconductor device connected to the first surface of the second substrate;

at least one first connector connected to a circuit on the second surface of the first substrate;

at least one second connector connected to a circuit on the first surface of the first substrate and a circuit on the second surface of the second substrate; and

an enclosure containing the first substrate and the second substrate therein, the enclosure having a portion thereof sealingly engaging a portion of the first substrate.

14. A semiconductor device assembly having a plurality of substrates comprising:

a first substrate having a first surface, a second surface, a plurality of circuits located on at least one of the first surface and the second surface, at least one circuit located on the first surface and the second surface;

a first semiconductor device located on the first surface of the first substrate, the semiconductor device having a first surface, a second surface, and a periphery, the second surface of the first semiconductor device connected to the first surface of the first substrate;

a second substrate having a first surface, a second surface, at least one circuit located on the first surface thereof, at least one aperture therein, and at least one alignment pin having a portion thereof secured in a portion of the at least one aperture;

a first heat transfer member having at least one aperture therein and at least one slot therein, the first heat transfer member in contact with a portion of the first semiconductor device, the at least one alignment pin of the second substrate configured to extend through the at least one aperture in the first heat transfer member; and

at least one connector extending between a circuit on the second surface of the first substrate and a circuit on the first surface of the second substrate.

20. A semiconductor device assembly comprising:

a first substrate having a first surface, a second surface, a plurality of circuits located on at least one of the first surface and the second surface, at least two circuits located on the first surface and the second surface;

a first semiconductor device located on the first surface of the first substrate, the semiconductor device having a first surface, a second surface, and a periphery, the second surface of the semiconductor device connected to the first surface of the first substrate;

a first heat transfer member having at least one aperture therein and at least one slot therein, the first heat transfer member in contact with a portion of the first semiconductor device, said first heat transfer member configured to extend substantially parallel and outwardly beyond a periphery of said first substrate;

at least one connector connected to a circuit on the second surface of the first substrate;

a second substrate having a first surface, a second surface, a plurality of circuits thereon, at least one circuit located on the first surface and the second surface;

a second semiconductor device located on the first surface of the second substrate, the second semiconductor device having a first surface, a second surface, and a periphery, the second surface of the semiconductor device connected to the first surface of the second substrate; and

at least one first connector is connected to a circuit on the first surface of the first substrate and a circuit on the second surface of the second substrate, the at least one connector configured to extend through the at least one slot in the first heat transfer member.

21. The semiconductor device assembly of claim 20, further comprising:

a second heat transfer member having at least one aperture therein and at least one slot therein, the second heat transfer member in contact with a portion of the second semiconductor device.

22. The semiconductor device assembly of claim 20, wherein the first heat transfer member includes at least one T-shaped portion and at least one L-shaped portion.

23. The semiconductor device assembly of claim 22, wherein a portion of the at least one T-shaped portion of the first heat transfer member retains a portion of the first substrate therein.

24. The semiconductor device assembly of claim 23, wherein a portion of the at least one L-shaped portion of the first heat transfer member retains a portion of the first substrate therein.

25. The semiconductor device assembly of claim 20, wherein the first heat transfer member includes at least one circular shaped heat transfer member.

26. The semiconductor device assembly of claim 20, wherein the first heat transfer member includes at least one elliptical shaped heat transfer member.

28. The semiconductor device assembly of claim 27, further comprising:

at least one fin connected to a portion of the enclosure.

30. The semiconductor device assembly of claim 29, further comprising:

a fourth substrate having a first surface, a second surface, a plurality of circuits thereon, at least one circuit located on the first surface and the second surface;

a third semiconductor device located on the first surface of the fourth substrate; and

at least one connector extending between a circuit on the first surface of the third substrate and a circuit on the second surface of the fourth substrate, the at least one connector extending through the at least one slot in the second heat transfer device.

31. The semiconductor device assembly of claim 30, further comprising:

a third heat transfer device in contact with the first surface of the third semiconductor device, the third heat transfer device having at least one aperture therein, the at least one alignment pin of the second substrate having a portion thereof extending into the at least one aperture in the third heat transfer device.

32. The semiconductor device assembly of claim 31, further comprising:

a fourth heat transfer device, the fourth heat transfer device in contact with a portion of the second surface of the fourth substrate and a portion of the first heat transfer device.

33. The semiconductor device assembly of claim 31, further comprising:

a fifth substrate having a first surface, a second surface, a plurality of circuits thereon, at least one circuit located on the first surface and the second surface;

a fourth semiconductor device located on the first surface of the fifth substrate;

another first heat transfer device having at least one aperture therein and at least one slot therein, the another first heat transfer device connected to the fourth semiconductor device, the at least one alignment pin of the second substrate extending through the at least one aperture in the another first heat transfer device;

at least one connector extending between a circuit on the first surface of the fourth substrate and a circuit on the second surface of the fifth substrate, the at least one connector extending through the at least one slot in the third heat transfer device; and

a fourth heat transfer device located on the at least one alignment pin of the second substrate, the fourth heat transfer device located between the first heat transfer device and the another first heat transfer device.

34. The semiconductor device assembly of claim 33, wherein the another first heat transfer device includes fins thereon.

27. A semiconductor device assembly having a plurality of substrates comprising:

a first substrate having a first surface, a second surface, a plurality of circuits located on one of the first surface and the second surface, at least one circuit located on the first surface and the second surface;

a first semiconductor device directly contacting the first surface of the first substrate, the semiconductor device having a first surface, a second surface, and a periphery, the second surface of the first semiconductor device connected to the first surface of the first substrate;

at least one connector connected to a circuit on the second surface of the first substrate;

a second substrate having a first surface, a second surface, a plurality of circuits thereon, at least one circuit located on the first surface and the second surface;

a second semiconductor device located on the first surface of the second substrate, the second semiconductor device having a first surface, a second surface, and a periphery, the second surface of the second semiconductor device connected to the first surface of the second substrate;

at least one first connector connected to a circuit on the second surface of the first substrate;

at least one second connector connected to a circuit on the first surface of the first substrate and a circuit on the second surface of the second substrate; and

an enclosure configured to contain the first substrate and the second substrate therein, the enclosure having a portion thereof configured to sealingly engage a portion of the first substrate.

29. A semiconductor device assembly having a plurality of semiconductor devices comprising:

a first substrate having a first surface, a second surface, a plurality of circuits located on one of the first surface and the second surface, at least one circuit located on the first surface and the second surface;

a first semiconductor device located on the first surface of the first substrate, the first semiconductor device having a first surface, a second surface, and a periphery, the second surface of the first semiconductor device connected to the first surface of the first substrate;

a second substrate having a first surface, a second surface, at least one circuit located on the first surface thereof, at least one aperture therein, and at least one alignment pin having a portion thereof secured in a portion of the at least one aperture;

a first heat transfer device having at least one aperture therein and at least one slot therein, the first heat transfer device in contact with a portion of the first semiconductor device, the at least one alignment pin of the second substrate extending through the at least one aperture in the first heat transfer device;

at least one connector extending between a circuit on the second surface of the first substrate and a circuit on the first surface of the second substrate;

a second semiconductor device located on the first surface of the second substrate, the second semiconductor device having a first surface, a second surface, and a periphery, the second surface of the second semiconductor device connected to the first surface of the second substrate;

a third substrate having a first surface, a second surface, at least one circuit located on the first surface thereof;

a second heat transfer device having at least one aperture therein and at least one slot therein, the second heat transfer device in contact with a portion of the second semiconductor device, the at least one alignment pin of the second substrate extending through the at least one aperture in the second heat transfer device; and

at least one connector extending between a circuit on the second surface of the third substrate and a circuit on the first surface of the first substrate.