Array substrate for a liquid crystal display device and method for fabricating thereof
First Claim
1. An array substrate, comprising:
- a substrate;
a first gate shorting bar on the substrate, the first gate shorting bar having a plurality of first connecting contact holes;
a second gate shorting bar spaced apart from and parallel to the first gate shorting bar, the second gate shorting bar having a plurality second connecting contact holes;
a plurality of gate lines on the substrate and perpendicular to the first and second gate shorting bars, the gate lines comprising odd numbered gate lines and even numbered gate lines;
a plurality of gate pads comprising odd numbered gate pads connected to the ends of odd numbered gate lines and even numbered gate pads connected to the ends of even numbered gate lines, wherein each gate pad of said plurality of gate pads has a corresponding gate pad contact hole;
a plurality of first pad connectors, each connecting an odd numbered gate pad to the first gate shorting bar via the corresponding gate pad contact hole and via a corresponding first connecting contact hole; and
a plurality of second pad connectors, each connecting an even numbered gate pad to the second gate shorting bar through the corresponding gate pad contact hole and via a corresponding second connecting contact hole.
2 Assignments
0 Petitions
Accused Products
Abstract
An LCD fabricated by forming gate lines, gate electrodes, gate pads, vertical patterns, and a first gate shorting bar on a substrate, forming channels over the gate electrodes, forming data lines, source electrodes, drain electrodes, and a second shorting bar, forming a passivation layer, patterning the passivation layer to form drain contact holes to the drain electrodes, data pad contact holes to the data pads, first connecting contact holes to the first gate shorting bar, second connecting contact holes to the second gate shorting bar, and etching holes to the vertical patterns, forming a transparent conductive layer, and patterning the transparent conductive layer to form pixel electrodes, first pad connectors that connect odd numbered gate pads to the first gate shorting bar, and second pad connectors that connect the even numbered gate pads to the second gate shorting bar, wherein the vertical patterns are etched via the etching holes.
36 Citations
18 Claims
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1. An array substrate, comprising:
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a substrate;
a first gate shorting bar on the substrate, the first gate shorting bar having a plurality of first connecting contact holes;
a second gate shorting bar spaced apart from and parallel to the first gate shorting bar, the second gate shorting bar having a plurality second connecting contact holes;
a plurality of gate lines on the substrate and perpendicular to the first and second gate shorting bars, the gate lines comprising odd numbered gate lines and even numbered gate lines;
a plurality of gate pads comprising odd numbered gate pads connected to the ends of odd numbered gate lines and even numbered gate pads connected to the ends of even numbered gate lines, wherein each gate pad of said plurality of gate pads has a corresponding gate pad contact hole;
a plurality of first pad connectors, each connecting an odd numbered gate pad to the first gate shorting bar via the corresponding gate pad contact hole and via a corresponding first connecting contact hole; and
a plurality of second pad connectors, each connecting an even numbered gate pad to the second gate shorting bar through the corresponding gate pad contact hole and via a corresponding second connecting contact hole. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A method of fabricating an array substrate, comprising:
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forming a first metal layer on a substrate;
patterning the first metal layer to form a first gate shorting bar, a vertical pattern, a plurality of odd gate lines, each having an associated odd gate pad and gate electrodes, and a plurality of even gate lines, each having an associated even gate pad and gate electrodes, wherein the vertical pattern electrically connects the odd gate pads and the even gate pads together;
forming a gate insulation layer over the substrate and over the patterned first metal layer;
forming an active layer and an ohmic contact layer over each gate electrode;
forming a second metal layer over the gate insulation layer and over the ohmic contact layers;
patterning the second metal layer to form a second shorting bar and a plurality of data lines, a plurality of source electrodes, and a plurality of drain electrodes, wherein each source electrode and each drain electrode is formed over an associated ohmic contact layer;
forming a passivation layer over the patterned second metal layer;
patterning the passivation layer to form drain contact holes to the drain electrodes, odd gate pad contact holes to the odd gate pads, even gate pad contact holes to the even gate pads, first connecting contact holes to the first gate shorting bar, second connecting contact holes to the second gate shorting bar, and etching holes to the vertical pattern;
forming a transparent conductive layer over the patterned passivation layer; and
patterning the transparent conductive layer to form pixel electrodes, first pad connectors that electrically connect the first gate shorting bar to associated odd gate pads via the first connecting contact holes and via the odd gate pad contact holes, and second pad connectors that electrically connect the second gate shorting bar to associated even gate pads via the second connecting contact holes and via the even gate pad contact holes;
wherein patterning the transparent conductive layer etches the vertical pattern via the etching holes such that the odd gate pads are electrically isolated from the even gate pads. - View Dependent Claims (8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18)
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Specification