METHOD FOR DRIVING SEMICONDUCTOR MEMORY

• US 20020027796A1
• Filed: 08/30/2001
• Published: 03/07/2002
• Est. Priority Date: 09/05/2000
• Status: Active Grant

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Kato, Yoshihisa, Shimada, Yasuhiro
• Granted Patent: US 6,388,915 B1
• Time in Patent Office: Days
• US Class Current: 365/145
• CPC Class Codes: G11C 11/22 using ferroelectric elements

Abstract

A cell selecting transistor serially connected to a data read ferroelectric capacitor selected from plural ferroelectric capacitors for data read is turned on and other cell selecting transistors serially connected to the other ferroelectric capacitors are turned off. Thus, one electrode of the data read ferroelectric capacitor is connected to a set line through a first common node, and the other electrode of the data read ferroelectric capacitor is connected to a load capacitor through a second common node. Next, after a reading voltage is applied to the set line so as to read a data stored in the data read ferroelectric capacitor, the reading voltage applied to the set line is removed. The reading voltage is set to such magnitude that displacement of polarization of the ferroelectric film of the data read ferroelectric capacitor is restored to that obtained before reading a data by removing the reading voltage.

Claims

1. A method for driving a semiconductor memory,

said semiconductor memory including a memory cell block composed of a plurality of memory cells connected to one another in parallel and each including a ferroelectric capacitor for storing a data in accordance with displacement of polarization of a ferroelectric film thereof and a cell selecting transistor connected to said ferroelectric capacitor in series;

a set line connected to a first common node of two common nodes included in said memory cell block, a reading voltage being applied to said set line; and

a load capacitor connected to a second common node of the two common nodes for detecting displacement of polarization of the ferroelectric film of a selected ferroelectric capacitor selected from a plurality of ferroelectric capacitors included in said plurality of memory cells, the method comprising;

a first step of turning on one of said cell selecting transistors serially connected to said data read ferroelectric capacitor and turning off the other of said cell selecting transistors serially connected to ferroelectric capacitors from which a data is not to be read among said plurality of ferroelectric capacitors, whereby connecting a first electrode of said data read ferroelectric capacitor to said set line through said first common node and connecting a second electrode of said data read ferroelectric capacitor to said load capacitor through said second common node;

a second step of applying a reading voltage to said set line; and

a third step of removing said reading voltage applied to said set line,

wherein said reading voltage applied in the second step is set to such magnitude that displacement of polarization of the ferroelectric film of said data read ferroelectric capacitor is restored to displacement obtained before reading a data by removing said reading voltage in the third step.

2. The method for driving a semiconductor memory of claim 1, further comprising, after the third step, a fourth step of making a potential difference caused between said first electrode and said second electrode of said data read ferroelectric capacitor zero.

3. The method for driving a semiconductor memory of claim 1,

wherein said reading voltage applied in the second step is set to such magnitude that a potential difference caused, in applying said reading voltage, between said first electrode and said second electrode of said data read ferroelectric capacitor is smaller than a coercive voltage of said data read ferroelectric capacitor.

4. The method for driving a semiconductor memory of claim 1,

wherein said plurality of ferroelectric capacitors are disposed on the side of said first common node and said plurality of cell selecting transistors are disposed on the side of said second common node.

5. The method for driving a semiconductor memory of claim 1,

wherein said load capacitor is a field effect transistor whose gate electrode is connected to said second common node.