Spread-spectrum high data rate system and method

• US 20020027948A1
• Filed: 10/02/2001
• Published: 03/07/2002
• Est. Priority Date: 11/04/1998
• Status: Active Grant

• Current Assignee: Zyrcuits IP LLC (IP Edge LLC)
• Original Assignee: Donald L. Schilling
• Inventors: Schilling, Donald L.
• Granted Patent: US 6,671,307 B2
• Time in Patent Office: Days
• US Class Current: 375/143
• CPC Class Codes: H04B 1/708 Parallel implementation
• CPC Class Codes: H04B 1/709 Correlator structure
• CPC Class Codes: H04B 1/7093 Matched filter type
• CPC Class Codes: H04L 1/004 by using forward error control H04L1/0618 takes precedence; coding, decoding or code conversion, for error detection or correction H03M13/00
• CPC Class Codes: H04L 1/0041 Arrangements at the transmitter end
• CPC Class Codes: H04L 1/0045 Arrangements at the receiver end
• CPC Class Codes: H04L 1/0071 Use of interleaving interleaving per se H03M13/27

Abstract

A high data rate, high processing gain, direct sequence spread spectrum system that transmits a BPSK or QPSK signal. The system FEC encodes and interleaves data which are collected and stored and forwarded N bits at a time by transmitting one of 2^N pseudo random waveforms every time N bits are collected. The 2^N pseudo random waveforms can be sent as an orthogonal, bi-orthogonal, or nearly orthogonal waveform. During acquisition, a plurality of product devices multiply a received spread-spectrum signal by a header chip-sequence signal. In each case, the header chip-sequence signal has a different delay, with each delay being at most one chip. Acquisition can also be achieved using a matched filter. After acquisition, the plurality of product device multiply the received spread-spectrum signal by 2^N chip-sequence signals to generate a plurality of products, with each chip-sequence signal of the plurality of chip-sequences signals being different from other chip-sequence signals of the plurality of chip-sequence signals; a plurality of integrators integrate the plurality of products thereby forming 2^N correlators, and a comparator selects a largest value from the plurality of integrators. The largest value is decoded into N bits of data. This process is repeated for each N bit word received.

Claims

1. A spread-spectrum system for sending data over a communications channel, comprising:

a forward-error-correction (FEC) encoder for encoding, with an FEC code, the data as FEC data;

an interleaver, coupled to said FEC encoder, for interleaving the FEC data as interleaved data;

a memory, coupled to said interleaver, for storing N bits of interleaved data as stored data, with N a number of bits in a symbol;

a chip-sequence encoder, coupled to said memory, for selecting, responsive to the N bits of stored data, a chip-sequence signal from 2^N chip-sequence signals stored in said chip-sequence encoder, as an output chip-sequence signal of said chip-sequence encoder;

a transmitter section, coupled to said chip-sequence encoder, for transmitting the output chip-sequence signal as a radio wave, at a carrier frequency, over said communications channel, as a spread-spectrum signal;

a receiver section, coupled to said communications channel, for translating the spread-spectrum signal to a processing frequency as a received spread-spectrum signal;

a plurality of product devices, coupled to said receiver section, for multiplying, at the processing frequency, for acquisition, the received spread-spectrum signal by a header chip-sequence signal with each chip-sequence signal having an identical chip sequence as the header chip-sequence signal, each chip-sequence signal having a delay of one-half or one chip, relative to one another and having a different delay from other chip-sequence signals;

said plurality of product devices for multiplying, after acquisition, the received spread-spectrum signal by the plurality of 2^N chip-sequence signals, with each chip-sequence signal from the plurality of 2^N chip-sequence signals having a different chip sequence from other chip-sequence signals in the plurality of 2^N chip-sequence signals, respectively;

a plurality of integrators coupled to said plurality of product devices, respectively, for integrating a plurality of products from the plurality of product devices during a period of a chip-sequence signal thereby forming 2^N correlators;

a comparator, coupled to said plurality of integrators, for selecting a largest value from the plurality of integrators;

a chip-sequence decoder, coupled to said comparator, for decoding the largest value from a respective integrator of said plurality of integrators, into N bits of interleaved data;

a deinterleaver, coupled to said chip-sequence decoder, for deinterleaving a series of interleaved bits from said chip-sequence decoder, as deinterleaved data; and

a FEC decoder, coupled to said deinterleaver, for FEC decoding the deinterleaved data as estimated data.

2. An improvement to a spread-spectrum system for sending data over a communications channel, comprising:

memory means for storing N bits of data as stored data, with N a number of bits in a symbol;

chip-encoder means, coupled to said memory means, for selecting, responsive to the N bits of stored data, a chip-sequence signal from a plurality of 2^N chip-sequence signals stored in said chip-sequence encoder, as an output chip-sequence signal of said chip-encoder means;

a transmitter section, coupled to said chip-encoder means, for transmitting the output chip-sequence signal as a radio wave, at a carrier frequency, over said communications channel, as a spread-spectrum signal;

a receiver section, coupled to said communications channel, for translating the spread-spectrum signal to a processing frequency as a received spread-spectrum signal;

spread-spectrum means, coupled to said receiver section, for processing, at the processing frequency, for acquisition, the received spread-spectrum signal by a header chip-sequence signal from the plurality of chip-sequence signals, with each chip-sequence signal of the plurality of chip-sequence signals set for having an identical chip sequence as the header chip-sequence signal, each chip-sequence signal having a delay of one-half or one chip, with each chip-sequence signal from the plurality of chip-sequence signals having a different delay from other chip-sequence signals, said spread-spectrum means for processing, after acquisition, the received spread-spectrum signal by the plurality of chip-sequence signals with each chip-sequence signal from the plurality of chip-sequence signals having a different chip sequence from other chip-sequence signals in the plurality of chip-sequence signals, respectively;

integrator means coupled to said spread-spectrum means, for integrating a plurality of output signals from said spread-spectrum means during a period of a chip-sequence signal;

comparator means, coupled to said integrator means, for selecting a largest value from said integrator means; and

chip-decoder means, coupled to said comparator means, for decoding the largest value from said integrator means into N bits of estimated data.

3. An improvement to a spread-spectrum system for sending data over a communications channel, comprising:

a memory for storing N bits of data as stored data, with N a number of bits in a symbol;

a chip-sequence encoder, coupled to said memory, for selecting, responsive to the N bits of stored data, a chip-sequence signal from a plurality of chip-sequence signals stored in said chip-sequence encoder, as an output chip-sequence signal;

a transmitter section, coupled to said chip-sequence encoder, for transmitting the output chip-sequence signal as a radio wave, at a carrier frequency, over said communications channel, as a spread-spectrum signal;

a receiver section, coupled to said communications channel, for translating the spread-spectrum signal to a processing frequency as a received spread-spectrum signal;

a plurality of product devices, coupled to said receiver section, for multiplying, at the processing frequency, for acquisition, the received spread-spectrum signal by a header chip-sequence signal from the plurality of chip-sequence signals, with each chip-sequence signal of the plurality of chip-sequence signals set having an identical chip sequence as the header chip-sequence signal, each chip-sequence signal having a delay of at most one chip, with each chip-sequence signal from the plurality of chip-sequence signals having a different delay from other chip-sequence signals, said plurality of product devices for multiplying, after acquisition, the received spread-spectrum signal by the plurality of chip-sequence signals, with each chip-sequence signal from the plurality of chip-sequence signals having a different chip sequence from other chip-sequence signals in the plurality of chip-sequence signals, respectively;

a plurality of integrators coupled to said plurality of product devices, respectively, for integrating a plurality of products from the plurality of product devices during a period of a chip-sequence signal;

a comparator, coupled to said plurality of integrators, for selecting a largest value from the plurality of integrators; and

a chip-sequence decoder, coupled to said comparator, for decoding the largest value from a respective integrator of said plurality of integrators, into N bits of interleaved data.

4. A spread-spectrum method improvement for sending data over a communications channel, comprising the steps of:

storing, at a transmitter, N bits of interleaved data as stored data, with N a number of bits in a symbol;

selecting, at said transmitter in response to the N bits of stored data, a chip-sequence signal from a plurality of 2^N chip-sequence signals, as an output chip-sequence signal;

transmitting, at said transmitter, the output chip-sequence signal as a radio wave, at a carrier frequency, over said communications channel, as a spread-spectrum signal;

translating, at a receiver, the spread-spectrum signal to a processing frequency as a received spread-spectrum signal;

multiplying, at the processing frequency, for acquisition, the received spread-spectrum signal by a header chip-sequence signal from the plurality of chip-sequence signals, with each chip-sequence signal of the plurality of 2^N chip-sequence signals set for having an identical chip sequence as the header chip-sequence signal, each chip-sequence signal having a delay of at most one chip, with each chip-sequence signal from the plurality of chip-sequence signals having a different delay from other chip-sequence signals;

multiplying, after acquisition, the received spread-spectrum signal by the plurality of chip-sequence signals, with each chip-sequence signal from the plurality of chip-sequence signals having a different chip sequence from other chip-sequence signals in the plurality of chip-sequence signals, respectively;

integrating a plurality of products from the plurality of product devices during a period of a chip-sequence signal;

selecting a largest value from the plurality of integrators; and

decoding the largest value from a respective integrator of said plurality of integrators into N bits of interleaved data.