Bias monitor for semiconductor burn-in

• US 20020030506A1
• Filed: 06/08/2001
• Published: 03/14/2002
• Est. Priority Date: 08/07/2000
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Vanguard International Semiconductor Corporation
• Inventors: Chen, Chung-Zen
• Granted Patent: US 6,650,105 B2
• Time in Patent Office: Days
• US Class Current: 324/765
• CPC Class Codes: G01R 31/2855 Environmental, reliability or burn-in testing
• CPC Class Codes: G01R 31/2879 related to electrical aspects, e.g. to voltage or current supply or stimuli or to electrical loads

Abstract

In this invention is described the use of an EPROM that is configred in a special way to monitor in situ the applied voltage to semiconductor product in a burn-in test and capture the maximum value of the applied voltage. during the test. This technique operates off the threshold shift mechanism in which gate bias induces electrons at the substrate surface which are accelerated by the drain and trapped in the polysilcon gate after the electrons overcome the gate oxide energy barrier. This puts an extra bias on the gate making a threshold voltage shift. The measurement of the threshold voltage shift for a particular period of time will be proportional to the value of the applied voltage. The trapped electrons can be released back to the substrate by use of ultra violet light since the electrons gain energy from the UV light to overcome the gate oxide energy barrier.

Claims

1. A voltage monitor for semiconductor burn in, comprising:

a) a burn-in board populated with semiconductor product,

b) said semiconductor product connected to a voltage bias and through isolation resistors connected to a driver board,

c) a specially configured EPROM connected to said voltage bias to continuously monitor said voltage bias during burn-in test of said semiconductor product,

d) said EPROM capturing and holding a maximum voltage occurrence during product burn-in.

2. The voltage monitor of claim 1, wherein the EPROM is configured with source and substrate connected to ground and gate and drain connected to the burn-in voltage bias.

3. The voltage monitor of claim 1, wherein the EPROM can be read out during and after said burn-in test of said semiconductor product.

4. The voltage monitor of claim 1, wherein said EPROM is connected to and monitors voltage bias distributed to all semiconductor product on said burn-in board where signal pins of said semiconductor product are connected to a burn-in driver board through an isolation resistor.

5. The voltage monitor of claim 1, wherein said EPROM is connected to and monitors voltage bias distributed to a row of semiconductor product on said burn-in board where signal pins of said row of semiconductor product are connected to a burn-in driver board through an isolation resistor.

6. The voltage monitor of claim 1, wherein said EPROM is connected to and monitors voltage bias distributed to each semiconductor product on said burn-in board where signal pins of each said semiconductor product are connected to a burn-in driver board through an isolation resistor.

7. An EPROM configuration to monitor a semiconductor burn-in bias voltage, comprising:

a) a source and substrate of said EPROM connected together and connected to circuit ground,

b) a gate and a drain of said EPROM connected together and connected to said burn-in bias voltage,

c) said burn-in bias voltage connected to semiconductor product in a burn-in test,

d) said bias voltage induces electrons at P-type substrate surface accelerated by drain bias, trapped in a polysilicon gate, and increasing gate threshold voltage,

e) burn-in bias noise causing an increase in voltage of said burn-in bias induces more electrons into said P-type substrate and subsequently further increases said gate threshold voltage.

8. The EPROM configuration of claim 7, wherein a burn-in bias noise causing a decrease in voltage of said burn-in bias does not change said gate threshold voltage.

9. The EPROM configuration of claim 7, wherein the gate threshold voltage can be measured during or after burn-in testing to determine a maximum applied bias voltage during burn-in.

10. The EPROM configuration of claim 7, wherein the gate threshold voltage caused by monitoring voltage during burn-in testing can be erased by exposing said EPROM to ultraviolet light.