Single horizontal scan range CRT monitor

• US 20020030695A1
• Filed: 06/13/2001
• Published: 03/14/2002
• Est. Priority Date: 10/21/1999
• Status: Active Grant

• Current Assignee: Saturn Licensing LLC (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.), Sony Electronics Inc. (Sony Group Corp.)
• Inventors: Narui, Yoshihisa, Espinosa, Pablo A.
• Granted Patent: US 6,816,131 B2
• Time in Patent Office: Days
• US Class Current: 345/698
• CPC Class Codes: G09G 1/167 Details of the interface to the display terminal specific for a CRT details suitable for both CRT and flat panel G09G5/006, specific for a flat panel G09G3/2096
• CPC Class Codes: G09G 2340/0407 Resolution change, inclusive of the use of different resolutions for different screen areas
• CPC Class Codes: G09G 2340/0414 Vertical resolution change
• CPC Class Codes: G09G 2340/0421 Horizontal resolution change
• CPC Class Codes: G09G 2360/02 Graphics controller able to handle multiple formats, e.g. input or output formats
• CPC Class Codes: H04N 7/0105 using a storage device with different write and read speed

Abstract

A single horizontal scan range CRT monitor that includes a receiver for receiving display signals in a digital format from an external source, the initial display signals having one of a plurality of input resolutions, and a converter connected to the receiver and supplied with the initial display signals for detecting the input resolution of the initial display signals and converting the initial display signals to digital output signals having an output resolution selected from a plurality of different output resolutions matched to the detected input resolution of the initial display signals, and wherein all of the plurality of output resolutions have a same horizontal resolution and all of the digital output signals have a same horizontal frequency.

Claims

1. A single horizontal scan range monitor supplied with initial display signals in a digital format from an external source, the initial display signals having one of a plurality of input resolutions and comprising:

a cathode ray tube (CRT) display having a single horizontal scanning frequency; and

a converter supplied with the initial display signals for detecting the input resolution of the initial display signals, converting the initial display signals to digital output signals having a different vertical output resolution selected from a plurality of different output resolutions matched to the detected input resolution of the initial display signals and the single horizontal scanning frequency of the CRT display and supplying the digital output signals to the CRT display.

2. A single horizontal scan range monitor according to claim 1, wherein the converter includes a frame memory.

3. A single horizontal scan range monitor according to claim 1, wherein the external source transmits the initial display signals in the digital format and the monitor includes a receiver for receiving the initial display signals and supplying them to the converter.

4. A single horizontal scan range monitor according to claim 3, wherein the receiver is a transition minimized differential scaling (TMDS) receiver.

5. A single horizontal scan range monitor according to claim 3, wherein the receiver is a low voltage differential signaling (LVDS) receiver.

6. A single horizontal scan range monitor according to claim 3, wherein the receiver is a low voltage differential signaling display interface (LDI) receiver.

7. A single horizontal scan range monitor according to claim 3, wherein the receiver is a gigabit video interface (GVIF) receiver.

8. A single horizontal scan range monitor according to claim 1, further comprising a digital to analog converter for converting the digital output signals to corresponding analog output signals.

9. A single horizontal scan range monitor according to claim 8, wherein the initial display signals and the digital output signals have corresponding red, green and blue components and wherein the digital to analog converter has separate converters for each color component.

10. A single horizontal scan range monitor according to claim 1, wherein the converter converts the initial digital display signals to digital output signals having one predetermined horizontal resolution regardless of the horizontal resolution of the initial digital display signals.

11. A single horizontal scan range monitor according to claim 1, wherein the converter includes a scaling circuit that converts the resolution of the initial display signals according to the following table:

13. A single horizontal scan range monitor according to claim 12 wherein the converter resides in the monitor.

14. A single horizontal scan range monitor according to claim 12 wherein the converter resides in the external source.

15. A single horizontal scan range monitor according to claim 12 wherein the display is a cathode ray tube (CRT).

16. A single horizontal scan range monitor according to claim 12, wherein the sector controller is supplied with the vertical sync signal from the display data input and the horizontal sync pulse from the horizontal sync generator.

17. A single horizontal scan range monitor according to claim 12, wherein the resolution detector is supplied with the horizontal sync signal and the vertical sync signal from the display data input.

18. A single horizontal scan range monitor according to claim 12, wherein the external source includes a transmitter for transmitting the initial display signals in the digital format and the display data input includes a receiver for receiving the initial display signals and supplying them to the converter.

19. A single horizontal scan range monitor according to claim 18, wherein the receiver outputs a transition minimized differential scaling (TMDS) clock signal to the clock output terminal of display data input.

20. A single horizontal scan range monitor according to claim 12, wherein the frame memory includes at least two memory banks that are alternately written to and read from, and a pair of address controllers for controlling the reading and writing of data to the memory banks.

21. A single horizontal scan range monitor according to claim 12, wherein the data output clock generator includes a phase locked loop (PLL) circuit supplied with the horizontal sync pulse and a multiplier factor that is a function of the single predetermined horizontal resolution, wherein the data output clock generator generates the data output clock at a frequency equal to the product of the single horizontal scanning frequency and the multiplier factor.

22. A single horizontal scan range monitor according to claim 12, wherein the horizontal sync generator generates horizontal sync pulses at a frequency of 80 kHz.

23. A single horizontal scan range monitor according to claim 12, wherein the vertical sync generator generates vertical sync pulses at a selected one of the following frequencies in correspondence with the resolution detection signal:

79.9 Hz, 95.1 Hz, 124.8 Hz, 98.9 Hz, 88.4 Hz, and 75.1 Hz.

24. A single horizontal scan range monitor according to claim 12, wherein the converter converts the resolution of the initial display signals according to the following table:

26. A method for adapting a single horizontal scan range monitor according to claim 25, wherein the converting step includes converting the initial display signals to digital output signals having a single, predetermined horizontal resolution, irrespective of the horizontal resolution of the initial display signals.

27. A method for adapting a single horizontal scan range monitor according to claim 25, wherein the converting step includes the steps of writing to and reading from a frame memory.

28. A method for adapting a single horizontal scan range monitor according to claim 25, further comprising the step of receiving the initial display signals from the computer.

29. A method for adapting a single horizontal scan range monitor according to claim 28, wherein the receiving step includes transition minimized differential scaling (TMDS).

30. A method for adapting a single horizontal scan range monitor according to claim 28, wherein the receiving step includes the step of low voltage differential signaling (LVDS).

31. A method for adapting a single horizontal scan range monitor according to claim 28, wherein the receiving step includes the step of low voltage differential signaling display interfacing (LDI).

32. A method for adapting a single horizontal scan range monitor according to claim 28, wherein the receiving step includes the step of gigabit video interfacing (GVIF).

33. A method for adapting a single horizontal scan range monitor according to claim 25, further comprising the step s of digital to analog converting the digital output signals to corresponding analog output signals.

34. A method for adapting a single horizontal scan range monitor according to claim 27, wherein the initial display signals and the digital output signals have corresponding red, green and blue components and wherein the digital to analog converting step includes separately digital to analog converting each color component.

35. A method for adapting a single horizontal scan range monitor according to claim 25, wherein the converting step includes a scaling step that converts the resolution of the initial display signals according to the following table:

37. A method for adapting a single horizontal scan range monitor according to claim 36, wherein the monitor is a cathode ray tube (CRT) monitor.

38. A method for adapting a single horizontal scan range monitor according to claim 36, wherein the clock from the receiving step is a transition minimized differential scaling (TMDS) clock signal.

39. A method for adapting a single horizontal scan range monitor according to claim 36, wherein the frame memory includes at least two memory banks, which are alternately written to and read from.

40. A method for adapting a single horizontal scan range monitor according to claim 36, further comprising the step of generating a data output clock using a phase locked loop (PLL) circuit as the product of the horizontal sync and a multiplier factor corresponding to the sum of the desired horizontal resolution and a horizontal blanking interval.

41. A method for adapting a single horizontal scan range monitor according to claim 36, wherein the horizontal sync-generating step generates horizontal sync pulses at a frequency of 80 kHz.

42. A method for adapting a single horizontal scan range monitor according to claim 36, wherein the vertical sync generating step generates vertical sync pulses at a selected one of the following frequencies in correspondence with the resolution detection signal:

79.9 Hz, 95.1 Hz, 124.8 Hz, 98.9 Hz, 88.4 Hz, and 75.1 Hz.

43. A method for adapting a single horizontal scan range monitor according to claim 36, wherein the converting step converts the resolution of the initial display signals according to the following table:

12. A single horizontal scan range monitor, comprising:

a display having a single horizontal scanning frequency;

a display data input for receiving, from an external source, initial display signals in a digital format and having one of a plurality of input resolutions, a clock signal, a horizontal sync signal, and a vertical sync signal;

a converter supplied with the initial display signals and the horizontal sync signal and vertical sync signal from the display data input for detecting the input resolution of the initial display signals and converting the initial display signals to digital display output signals having a vertical output resolution selected from a plurality of different output resolutions matched to the detected input resolution of the initial display signals and the single horizontal scanning frequency of the display;

wherein the converter comprises;

a frame memory;

a resolution detector for detecting the resolution of the initial display signals and outputting a resolution detection signal;

a first multiplexer connected between the display data input, the frame memory, and the display for switching between writing the initial display signals into the frame memory and reading the digital display output signals out of the frame memory to the display;

an address counter controller for controlling the addresses at which data are written into the frame memory and read out from the frame memory;

a vertical sync generator connected to the resolution detector for generating a vertical sync pulse at a selected one of a plurality of vertical sync frequencies as a function of the detected resolution of the initial display signals;

a horizontal sync generator for generating a horizontal sync pulse at the single horizontal scanning frequency;

a data output clock generator for generating a data output clock signal as a function of the single horizontal scanning frequency and the horizontal resolution of the digital display output signals;

a second multiplexer connected between a clock output terminal of display data input, a vertical sync signal output of the display data input, the address counter, the data output clock signal generator, and the horizontal sync generator for selectively supplying to the address counter controller either the combination of the vertical sync signal and the clock from the display data input or the combination of the data output clock signal from the data output clock generator and the horizontal sync pulse from the horizontal sync generator; and

a sector controller for controlling the first multiplexer and the second multiplexer to synchronously and alternately write the initial display data to the frame memory at an initial resolution and scanning frequencies and read the digital output data signals from the frame memory to the display at resolutions and scanning frequencies different from those of the initial display data and matched to the requirements of the display.

25. A method for adapting a single horizontal scan range monitor having a single horizontal scanning frequency to receive and then display initial display signals generated by a computer in a digital format having one of a plurality of input resolutions, comprising the steps of:

detecting the input resolution of the initial display signals;

converting the initial display signals to digital output signals having a vertical output resolution selected from a plurality of different output resolutions matched to the detected input resolution of the initial display signals and the single horizontal scanning frequency; and

supplying the digital output signals to the monitor for display.

36. A method for adapting a single horizontal scan range monitor having a single horizontal scanning frequency to receive and then display initial display signals generated by a computer in a digital format having one of a plurality of input resolutions, comprising the steps of:

receiving the initial display signals and then outputting the initial display signals with the one of the plurality of input resolutions, and additionally outputting a clock signal, a horizontal sync signal, and a vertical sync signal;

detecting the input resolution of the initial display signals;

converting the initial display signals to digital output signals having an output vertical resolution selected from a plurality of different output resolutions matched to the detected input resolution of the initial display signals, a single, predetermined horizontal resolution, and the single horizontal scanning frequency; and

supplying the digital output signals to the monitor;

wherein the converting step comprises the steps of;

alternately writing the initial display signals into a frame memory and reading the digital output signals out of the frame memory;

controlling the addresses at which data are written into the frame memory and read out from the frame memory by means of an address counter controller;

generating a vertical sync pulse at a selected one of a plurality of vertical sync frequencies compatible with the monitor as a function of the detected resolution of the initial display signals;

generating a horizontal sync pulse at the single horizontal scanning frequency;

generating a data output clock; and

selectively supplying to the address counter controller either the combination of the vertical sync signal and clock from the initial display data generating step or the combination of a data output clock from the data output clock generating step and a horizontal sync pulse from the horizontal sync pulse generating step to the address counter controller to synchronously and alternately write the initial display data to the frame memory and read the digital output data signals from the frame memory to the monitor.