OPTICAL DRIVE CONTROLLER WITH A HOST INTERFACE FOR DIRECT CONNECTION TO AN IDE/ATA DATA BUS

• US 20020032808A1
• Filed: 06/28/1996
• Published: 03/14/2002
• Est. Priority Date: 06/22/1994
• Status: Active Grant

• Current Assignee: Mike Case, Phil Verinsky
• Original Assignee: Mike Case, Phil Verinsky
• Inventors: VERINSKY, PHIL, CASE, MIKE
• Granted Patent: US 6,584,527 B2
• Time in Patent Office: Days
• US Class Current: 710/5
• CPC Class Codes: G06F 3/0601 Interfaces specially adapted for storage systems
• CPC Class Codes: G06F 3/0607 by facilitating the process of upgrading existing storage systems, e.g. for improving compatibility between host and storage device
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0613 in relation to throughput
• CPC Class Codes: G06F 3/0626 Reducing size or complexity of storage systems
• CPC Class Codes: G06F 3/0638 Organizing or formatting or addressing of data
• CPC Class Codes: G06F 3/0656 Data buffering arrangements
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0661 Format or protocol conversion arrangements
• CPC Class Codes: G06F 3/0673 Single storage device
• CPC Class Codes: G06F 3/0677 Optical disk device, e.g. CD-ROM, DVD
• CPC Class Codes: G11B 2220/213 Read-only discs
• CPC Class Codes: G11B 2220/2545 CDs
• CPC Class Codes: G11B 27/105 of operating discs

Abstract

A compact disk drive controller to control the access of information from an optical compact disk (CD) digital data storage device by a host computer using an integrated drive electronics (IDE) data bus or an industry standard architecture (ISA) data bus is disclosed. A digital signal processor (DSP) interface to the drive electronics of the CD drive, a dynamic random access memory (DRAM) controller, an error correction code (ECC) data corrector, an error detection and correction (EDC) device employing cyclical redundancy checking techniques (EDC/CRC), and a host computer interface are described.

Claims

1. A compact disk drive controller for a compact disk drive to control the communication of digital information between a compact disk and a host computer, said compact disk drive having drive electronics including a digital signal processor, a microcontroller, a random access memory and a system controller, wherein said host computer communicates with said compact disk drive controller via an IDE data bus and receives digital information from the compact disk via said IDE data bus, said compact disk drive controller comprising:

a host interface connecting said host computer via said IDE data bus with said compact disk drive controller, to receive data addresses and commands from said host computer and to transmit digital information to said host computer,

a path for communicating data addresses and commands from said host interface to the microcontroller of said drive electronics, and

a digital signal processor interface connecting said host interface and said digital signal processor of said drive electronics to receive digital information from said compact disk and to transmit said digital information to said host interface.

2. The compact disk drive controller of claim 1, wherein said digital signal processor interface further comprises a descrambler to descramble and assemble the digital information received from said digital signal processor and store said digital information into said random access memory.

3. The compact disk drive controller of claim 1, wherein said digital signal processor interface further comprises an error correction code circuit to perform error correction on said digital information.

4. The compact disk drive controller of claim 3, wherein said error correction code circuit performs Reed-Solomon error correction on said digital information.

5. The compact disk drive controller of claim 3, wherein said digital signal processor interface further comprises a cyclic redundancy checker for detecting errors in said digital information after correction of said digital information by said error correction code circuit.

6. The compact disk drive controller of claim 1, wherein said host interface receives data addresses and commands from said host computer via said ISA data bus and communicates digital information to said host computer via said ISA bus.

7. The compact disk drive controller of claim 1, wherein said host interface further comprises a command FIFO to transfer commands from the host computer to the system controller of said drive electronics of said compact disk drive.

8. The compact disk drive controller of claim 1, wherein said host interface further comprises a status FIFO to transfer status information from said drive electronics of said compact disk drive to said host computer.

9. The compact disk drive controller of claim 1, wherein said drive electronics of said compact disk drive further comprises an ISA data bus and said host interface further comprises a configuration register via which said host computer instructs said compact disk drive controller to present said digital information onto one of said ISA and IDE data buses in a data format selected from a group including 16-bit DMA, 8-bit DMA, 16-bit PIO, and an 8-bit PIO format.

10. In a disk drive controller comprising a host interface and a digital signal processor interface, a method of controlling the communication of digital information between a host computer with an IDE data bus and a compact disk, comprising the steps of:

receiving commands from said host computer via said IDE data bus;

receiving data from a digital signal processor of a compact disk drive; and

communicating said data via said IDE data bus to said host computer.

11. The method of claim 11 wherein data received from said digital signal processor is corrected before being communicated to via said IDE data bus to said host computer.