Image sensors with pixel reset

• US 20020033439A1
• Filed: 05/16/2001
• Published: 03/21/2002
• Est. Priority Date: 05/16/2000
• Status: Active Grant

• Current Assignee: Aptina Imaging Corporation (ON Semiconductor Corporation)
• Original Assignee: Micron Technology, Inc.
• Inventors: Bock, Nikolai E.
• Granted Patent: US 7,274,396 B2
• Time in Patent Office: Days
• US Class Current: 250/208.1
• CPC Class Codes: H04N 25/65 applied to reset noise, e.g. KTC noise related to CMOS structures by techniques other than CDS

Abstract

Techniques for use with image sensors include transferring a signal level from an active sensor pixel to a readout circuit, performing a flushed reset of the pixel, and isolating the pixel from the readout circuit during resetting of the pixel.

Claims

1. A method comprising:

transferring a signal level from an active sensor pixel to a readout circuit;

performing a flushed reset of the pixel; and

electrically isolating the pixel from the readout circuit during resetting of the pixel.

2. The method of claim 1 wherein isolating the pixel includes disabling a transistor switch when the pixel is reset.

3. The method of claim 1 wherein isolating the pixel includes disabling the transistor switch for the duration of the flushed reset.

4. The method of claim 1 wherein isolating the pixel includes disabling a pixel row selection switch.

5. The method of claim 1 including preventing a parasitic output capacitance from discharging through a load transistor in the readout circuit during the reset.

6. The method of claim 5 wherein preventing the parasitic output capacitance from discharging includes disabling a transistor switch coupled between the load transistor and an output of the pixel.

7. The method of claim 1 wherein isolating the pixel includes disabling the transistor switch for the duration of the flushed reset, the method further including preventing a parasitic output capacitance from discharging through a load transistor in the readout circuit during the reset.

8. The method of claim 1 wherein performing a flushed reset includes performing a hard reset followed by a soft reset.

9. The method of claim 1 wherein performing a flushed reset includes discharging a power supply capacitance present at a node coupled to a drain of a pixel reset switch.

10. An integrated circuit chip comprising:

an array of active sensor pixels each of which is associated with a row and a column in the array, each pixel including a reset switch and a row selection switch;

readout circuits each of which is associated with and is coupled to a respective subset of pixels in the array; and

a controller for providing a first control signal to enable the row selection switches in a selected row of pixels to transfer signal levels from the pixels in the selected row to the associated readout circuits, for subsequently providing a second control signal to enable the reset switches in the selected row of pixels, and for causing the first control signal to disable the row selection switches in the selected row of pixels during resetting of the pixels in the selected row.

11. The integrated circuit chip of claim 10, each readout circuit including circuitry for performing a flushed reset of the pixels associated with that readout circuit when a third control signal from the controller is pulsed while the second control signal enables the reset switches in the selected row of pixels.

12. The integrated circuit chip of claim 11:

each pixel including a source-follower transistor coupled to the photodiode;

each readout circuit including;

a load transistor for the source-follower transistor in the pixels associated with the readout ciruit; and

a switch coupled in series with the load transistor and coupled between the load transistor and an output of the pixels in the associated columns;

the controller providing a control signal for disabling the switch coupled in series with the load transistor during resetting of the pixels.

13. The integrated circuit chip of claim 10 wherein each pixel includes a photodiode.

15. The integrated circuit chip of claim 14 including means for preventing a parasitic output capacitance from discharging through the load transistors in the readout circuits during resetting of the pixels.

14. An integrated circuit chip comprising:

an array of active sensor pixels each of which is associated with a row and a column in the array, each pixel including a photosensitive element, a source-follower transistor coupled to an output of the photosensitive element, a reset switch and a row selection switch;

readout circuits, each of which is associated with and is coupled to a respective column of pixels in the array, each readout circuit including a load transistor for source-follower transistors in the pixels in the associated column;

means for causing flushed reset of pixels in a selected row; and

means for isolating pixels in the selected row from the associated readout circuits during resetting of the pixels.