Insulated-gate field-effect transistor integrated with negative differential resistance (NDR) FET

• US 20020048190A1
• Filed: 12/21/2001
• Published: 04/25/2002
• Est. Priority Date: 06/22/2000
• Status: Active Grant

• Current Assignee: Synopsys Incorporated
• Original Assignee: Progressant Technologies, Inc. (Synopsys Incorporated)
• Inventors: King, Tsu-Jae
• Granted Patent: US 6,754,104 B2
• Time in Patent Office: Days
• US Class Current: 365/185.18
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: G11C 11/39 using thyristors or the avalanche or negative resistance type, e.g. PNPN, SCR, SCS, UJT
• CPC Class Codes: G11C 5/142 Contactless power supplies, e.g. RF, induction, or IR
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/788 with floating gate H01L29/78391 takes precedence
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors

Abstract

A semiconductor device is disclosed that includes integrated insulated-gate field-effect transistor (IGFET) elements and one or more negative differential resistance (NDR) field-effect transistor elements, combined and formed on a common substrate. Thus, a variety of circuits, including logic and memory are implemented with a combination of conventional and NDR capable FETs. Because both types of elements share a number of common features, they can be fabricated with common processing operations to achieve better integration in a manufacturing facility.

Claims

1. A semiconductor device comprising:

one or more insulated-gate field-effect transistor (IGFET) elements; and

one or more negative differential resistance field-effect transistor (NDR-FET) elements;

wherein at least some of said one or more IGFET elements are coupled to at least some of said one or more NDR FET elements;

further wherein at least some of said one or more IGFET elements and at least some of said one or more NDR-FET are formed by and within one or more common physical regions and/or layers associated with a single semiconductor die.

2. The device of claim 1, wherein the semiconductor device includes one or more electronic gates and/or circuits including:

a first type of gate and/or circuit formed exclusively of IGFET elements; and

a second type of gate and/or circuit formed from a combination of interconnected IGFET elements and NDR FET elements.

3. The device of claim 2, wherein the semiconductor device includes a third type of gate and/or circuit formed exclusively of NDR FET elements.

4. The device of claim 2, wherein said second type of gate and/or circuit includes a bi-stable memory cell and/or latch.

5. The device of claim 4, wherein said bi-stable latch includes an n channel IGFET element connected by a common control node in series to an n channel NDR FET element.

6. The device of claim 5, wherein said n channel IGFET is configured as an enhancement mode device with an IGFET drain terminal and IGFET gate terminal coupled to a first voltage potential and an IFGET source terminal coupled to said common control node, and said n channel NDR FET element includes an NDR FET gate terminal coupled to a bias voltage, an NDR FET drain terminal coupled to said common control node, and an NDR source terminal coupled to a second voltage potential.

7. The device of claim 5, wherein said n channel IGFET is configured as an enhancement mode device with an IGFET drain terminal and IGFET gate terminal coupled to said common control node and an IFGET source terminal coupled to a first voltage potential, and said n channel NDR FET element includes an NDR FET gate terminal coupled to a bias voltage, an NDR FET drain terminal coupled to a second voltage potential, and an NDR source terminal coupled to said common control node.

8. The device of claim 5, wherein said n channel IGFET is configured as a depletion mode device with an IGFET source terminal and IGFET gate terminal coupled to said common control node and an IFGET drain terminal coupled to a first voltage potential, and said n channel NDR FET element includes an NDR FET gate terminal coupled to a bias voltage, an NDR FET source terminal coupled to a second voltage potential, and an NDR drain terminal coupled to said common control node.

9. The device of claim 5, wherein said n channel IGFET is configured as a depletion mode device with an IGFET source terminal and IGFET gate terminal coupled to a first voltage potential, and an IFGET drain terminal coupled to said common control node, and said n channel NDR FET element includes an NDR FET gate terminal coupled to a bias voltage, an NDR FET source terminal coupled to said common control node, and an NDR drain terminal coupled to a second voltage potential.

10. The device of claim 4, further including an IGFET element configured as a transfer gate, such that a first source/drain terminal of said IGFET element is coupled to a first control node, a second source/drain terminal of said IGFET element is coupled to a second control node adapted for reading data from and/or writing data to said first control node, and an IGFET gate terminal for said IGFET element is coupled to an access signal;

and further including a first NDR FET with a first NDR FET gate terminal coupled to a first bias voltage, a first NDR FET drain terminal of said first NDR FET coupled to said first control node, and a first NDR source terminal of said first NDR FET coupled to a first voltage potential; and

further including a second NDR FET with a second NDR FET gate terminal coupled to a second bias voltage, a second NDR FET drain terminal of said second NDR FET coupled to a second voltage potential, and a second NDR source terminal of said second NDR FET coupled to said first control node.

11. The device of claim 10, wherein said first bias voltage and said second bias voltage are the same.

12. The device of claim 10, wherein said first bias voltage and said second voltage potential are the same.

13. The device of claim 10, wherein said second bias voltage is substantially larger than said first bias voltage.

14. The device of claim 1, wherein the semiconductor device includes a combination of logic circuits and embedded memory circuits that are implemented at least in part by NDR FET elements.

15. The device of claim 1, wherein portions of said one or more IGFET elements and said one or more NDR elements are formed at the same time during a semiconductor manufacturing process on a common substrate.

16. The device of claim 15, wherein said common substrate includes a silicon based wafer.

17. The device of claim 1, wherein IGFET source/drain regions for at least some of said one or more IGFET elements are common to and used as source/drain regions by at least some of said one or more NDR FET elements.

19. The device of claim 18, wherein said first circuit and said second circuit are the same.

20. The device of claim 19, wherein said first circuit and said second circuit are a memory cell.

21. The device of claim 18, wherein said NDR FET and said IGFET also share a common isolation area formed in said common substrate.

22. The device of claim 18, wherein said NDR FET element includes an additional gate insulation layer in addition to said common gate insulation layer.

23. The device of claim 18, wherein said common substrate is a silicon or silicon-germanium based substrate.

24. The device of claim 18, wherein said IGFET element and said NDR FET element further share a common source/drain region.

27. The method of claim 26, wherein said semiconductor die includes a semiconductor substrate and one or more distinctly doped regions in said semiconductor substrate used by both said IGFETs and said NDR FETs.

28. The method of claim 27, wherein said semiconductor die further includes one or more patterned thin film layers formed on said semiconductor substrate and used by both said IGFETs and said NDR FETs.

29. The method of claim 26, wherein said one or more common operations includes a step of forming isolation regions between both IGFETs and NDR-FETs.

30. The method of claim 26, wherein said one or more common operations includes a step of forming active areas, said active areas including IGFET source/drain regions for an insulated gate field effect transistor (IGFET) and NDR-FET source/drain regions for a negative differential resistance field effect transistor (NDR-FET).

31. The method of claim 30, wherein said active areas include one or more layers of silicon germanium.

32. The method of claim 26, wherein said one or mote common operations includes a step of forming gate insulation layers for both said IGFETs and said NDR-FETs.

33. The method of claim 26, wherein an IGFET gate insulation layer is formed using a different set of processing operations than those used for forming an NDR FET gate insulation layer.

34. The method of claim 33, wherein said IGFET gate insulation layer is substantially thinner than said NDR FET gate insulation layer.

35. The method of claim 33, wherein at least a part of said NDR FET gate insulation layer is formed prior to said IGFET gate insulation layer.

36. The method of claim 33, wherein said NDR FET gate insulation layer and said IGFET gate insulation layer include a common gate-dielectric layer, and said NDR FET gate insulation layer further includes an additional gate-dielectric layer.

37. The method of claim 36 further including a step of forming a charge trap layer within said additional gate-dielectric layer or at the interface between the gate insulating film and a channel of the NDR-FET.

38. The method of claim 37 further including a step of forming an additional common gate-dielectric layer over said additional gate-dielectric layer of said NDR FETs and said common gate-dielectric layer of said NDR FETs and IGFETs.

39. The method of claim 37, wherein said charge trap layer is formed by implantation in regions of said NDR FETs and/or oxidation of doped channel regions of said NDR FETs.

40. The method of claim 39, wherein said implantation uses boron, phosphorus, arsenic, fluorine, silicon, germanium, nitrogen or a metallic species.

41. The method of claim 26, wherein said one or more common operations includes a step of forming gate electrodes for both said IGFETs and said NDR-FETs.

42. The method of claim 41, wherein said gate electrodes are formed of polysilicon and/or polysilicon-germanium.

43. The method of claim 31, wherein said one or more common operations includes a step of forming contacts to both said IGFET source/drain regions and said NDR FET source/drain regions.

44. The method of claim 26, wherein said first set of operations include a first implant operation for an IGFET threshold adjustment, and said second set of operations include a second implant operation for an NDR FET threshold adjustment, and further wherein said first implant operation and said second implant operation are performed separately.

45. The method of claim 44, wherein said first implant operation and said second implant operation use different dopant species.

46. The method of claim 44, wherein IGFET channel regions are formed with a substantially different doping profile than NDR FET channel regions.

47. The method of claim 26, wherein said second set of operations include a step of forming a charge trap layer for said NDR FETs within a gate insulating film or at the interface between said gate insulating film and a semiconductor channel of the NDR-FETs.

18. An semiconductor device comprising:

an insulated-gate field-effect transistor (IGFET) element used in a first circuit; and

a negative differential resistance field-effect transistor NDR-FET) element used in a second circuit;

said IGFET element and said NDR FET element sharing at least;

(a) a common gate insulation layer; and

(b) a common substrate.

25. A semiconductor wafer comprising:

a plurality of semiconductor die;

each of said plurality of semiconductor die including;

(a) one or more insulated-gate field-effect transistor (IGFET) elements; and

(b) one or more negative differential resistance field-effect transistor (NDRFET) elements; and

wherein at least some of said one or more IGFET elements are coupled to at least some of said one or more NDR FET elements;

further wherein at least some of said one or more IGFET elements and at least some of said one or more NDR-FET are comprised of one or more common physical regions and/or layers associated with the semiconductor wafer.

26. A method of fabricating a semiconductor device comprising the steps of:

(a) providing a semiconductor die;

(b) forming insulated gate field effect transistors (IGFETs) in and/or on said semiconductor die during a first set of processing operations;

(c) forming negative differential resistance field effect transistors (NDR-FETs) in and/or on said semiconductor die during a second set of processing operations;

wherein said first set of processing operations and said second set of processing operations include one or more common operations so that portions of some of said IGFETs and portions of at least some of said NDR-FETs are formed at the same time during said one or more common operations.