SEMICONDUCTOR MEMORY PROVIDED WITH DATA-LINE EQUALIZING CIRCUIT
First Claim
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1. A semiconductor device operating under reception of an external power-supply voltage comprising:
- first and second data lines for transmitting a data signal having two data levels one of which corresponds to a first voltage; and
a plurality of memory cells for holding said data signal, each of said plurality of memory cells including a storage node for storaging the data level of said data signal, a data transfer gate for electrically connecting said storage node with one of said first and second data lines in response to activation of a word line set to a second voltage higher than said first voltage, and a data-line equalizing circuit for setting said first and second data lines to one same predetermined voltage in response to a control signal, said control signal being set to a third voltage higher than said external power-supply voltage and lower than said second voltage under activation.
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Abstract
An equalizing circuit includes a plurality of N-channel MOS transistors for respectively setting a data line to a predetermined precharge voltage. The H-level voltage Vddb of a control signal for turning on these N-channel MOS transistors is set to a range higher than the sum of the precharge voltage and a transistor threshold voltage. A Vddb generation circuit steps up an external power-supply voltage and sets a voltage Vddb in a range lower than a step-up voltage for activating a word line.
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Citations
16 Claims
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1. A semiconductor device operating under reception of an external power-supply voltage comprising:
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first and second data lines for transmitting a data signal having two data levels one of which corresponds to a first voltage; and
a plurality of memory cells for holding said data signal, each of said plurality of memory cells including a storage node for storaging the data level of said data signal, a data transfer gate for electrically connecting said storage node with one of said first and second data lines in response to activation of a word line set to a second voltage higher than said first voltage, and a data-line equalizing circuit for setting said first and second data lines to one same predetermined voltage in response to a control signal, said control signal being set to a third voltage higher than said external power-supply voltage and lower than said second voltage under activation. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A semiconductor device comprising:
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a memory cell including a capacitor for storing charges and an access transistor;
a data line pair including two data lines, one of said two data lines connected to said memory cell;
a word line connected to the gate of said access transistor, being set to a first voltage under activation;
a sense-amplifier circuit for amplifying a small voltage difference between said two data lines, said small voltage difference being generated representing the stored charges in said capacitor in response to the activation of said word line, to a voltage difference between the ground voltage and a second voltage; and
a data-line equalizing circuit for setting each of said two data lines to one same predetermined voltage in response to a control signal, said control signal being set to a third voltage higher than an external power-supply voltage and lower than said first voltage under activation.
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Specification