Variable attack & release system and method

• US 20020051546A1
• Filed: 11/29/2000
• Published: 05/02/2002
• Est. Priority Date: 11/29/1999
• Status: Active Grant

• Current Assignee: Karl M. Bizjak
• Original Assignee: Karl M. Bizjak
• Inventors: Bizjak, Karl M.
• Granted Patent: US 7,212,640 B2
• Time in Patent Office: Days
• US Class Current: 381/106
• CPC Class Codes: G10L 21/0232 Processing in the frequency domain
• CPC Class Codes: H03G 3/3089 Control of digital or coded signals
• CPC Class Codes: H03G 3/32 the control being dependent upon ambient noise level or sound level
• CPC Class Codes: H03G 7/002 in untuned or low-frequency amplifiers, e.g. audio amplifiers H03G7/007, H03G7/001, H03G7/008, H03G7/02, H03G7/06 take precedence
• CPC Class Codes: H03G 7/007 of digital or coded signals
• CPC Class Codes: H03G 7/06 having semiconductor devices
• CPC Class Codes: H03G 9/005 of digital or coded signals
• CPC Class Codes: H03G 9/025 frequency-dependent volume compression or expansion, e.g. multiple-band systems H03G9/10, H03G9/18 take precedence
• CPC Class Codes: H04R 2227/005 Audio distribution systems for home, i.e. multi-room use
• CPC Class Codes: H04R 25/356 Amplitude, e.g. amplitude shift or compression
• CPC Class Codes: H04R 27/00 Public address systems circuits for preventing acoustic reaction H04R3/02; circuits for distributing signals to loudspeakers H04R3/12; monitoring or testing arrangements for public address systems H04R29/007; amplifiers H03F
• CPC Class Codes: H04R 3/002 Damping circuit arrangements for transducers, e.g. motional feedback circuits

Abstract

Variable attack and release system and method are disclosed for dynamically modifying the various elements of the system including modifying compander response time to dynamically adjust for changing parameters such as environmental or input signal changes to maintain output signals within predetermined limits. The system and method include permitting accurate and quick response to noise sources having a duration which exceeds a predetermined threshold while at the same time ignoring transient or short duration environmental noise.

Claims

1. A signal processor system comprising

a power estimation signal,

a variable attack and release stage for detecting changes in amplitude of the power estimation signal relative to time,

comparing the changes in amplitude relative to time to a first criteria,

applying a first algorithm if the change in amplitude does not meet the first criteria,

applying a second algorithm if the change in amplitude does meet the first criteria.

2. The signal processor of claim 1 wherein the first algorithm includes a factor representing the amount of compression in the system.

3. The signal processor of claim 1 wherein the first algorithm includes a factor representing the amount of expansion in the system.

4. The signal processor of claim 1 wherein the first algorithm includes a factor representing user preference.

5. The signal processor of claim 1 wherein the detected change in amplitude is positive.

6. The signal processor of claim 1 wherein the detected change in amplitude is negative.

7. The signal processor of claim 5 wherein the first algorithm includes a first factor representing representing the amount of compression or expansion in the system.

8. The signal processor of claim 7 wherein the first algorithm includes a second factor representing user preference.

9. The signal processor of claim 6 wherein the detected change in amplitude is negative.

10. The signal processor of claim 9 wherein the second algorithm includes a first factor representing the amount of compression or expansion in the system.

11. The signal processor of claim 10 wherein the second algorithm includes a second factor representing user preference.

12. The signal processor system of claim 1 wherein the power estimation signal comprises a plurality of power estimation signals.

14. The variable attack and release processor of claim 13 further comprising

a second stage for modifying the first algorithm in accordance with at least one of a plurality of secondary characteristics, selected from a group comprising at least one of system parameter signals, user preference signals, feedback signal, and a characteristic of the input signal, a second plurality of algorithms.

15. The variable attack and release processor of claim 14 wherein the first algorithm includes a plurality of elements in a lookup table.

16. The variable attack and release processor of claim 15 wherein the second stage modifies the first algorithm by causing the selection of different entries in the lookup table.

17. The variable attack and release processor of claim 14 wherein the first algorithm is generated by combinatorial logic.

19. The variable attack and release processor of claim 18 wherein the algorithm values are directly calculated.

20. The processor of claim 13 wherein the first characteristic is a deviation signal between the current input and the current output.

21. The processor of claim 13 wherein the first characteristic is one of a group of logic states comprising attack, release, and a transition between the two.

22. The processor of claim 13 wherein the first plurality of algorithms includes filters, linear and non-linear integrators, and time delays.

23. The processor of claim 14 wherein the first stage output signal comprises a plurality of processed deviation signals.

24. The processor of claim 13 wherein the input signal includes a plurality of incoming signals.

25. The processor of claim 13 wherein the feedback signal includes a plurality of feedback signals.

26. The processor of claim 13 wherein the comparison stage includes a plurality of comparison sub-stages.

27. The processor of claim 13 wherein the first stage includes a plurality of first sub-stages.

28. The processor of claim 26 wherein the first stage includes a plurality of first sub-stages.

29. The processor of claim 13 wherein the first stage output signal comprises a plurality of coefficients.

30. The processor of claim 14 wherein the first stage output signal comprises a plurality of coefficients resulting from the first stage as modified by the second stage.

31. The processor of claim 13 wherein the comparison stage further outputs at least one variable.

32. The processor of claim 31 wherein the comparison stage further outputs a plurality of control variables.

33. The processor of claim 31 wherein the control variables and coefficients are processed in at least one transform stage in a predetermined manner.

34. The processor of claim 33 wherein the transform stage implements at least one polynomial equation.

35. The processor of claim 33 wherein the transform stage processes the control variables and coefficients in accordance with at least one further lookup table.

36. The processor of claim 33 wherein the transform stage comprises a plurality of sub-transform stages.

37. The processor of claim 36 wherein each of the plurality of sub-transform stages implements a polynomial.

38. The processor of claim 37 where each of the polynomials is unique.

39. The processor of claim 36 further comprising

a combiner stage for combining outputs from at least two of the sub-transform stages.

40. The processor of claim 13 further including a tracking filter responsive to the first stage output signal and having an output.

41. The processor of claim 33 further including a tracking filter responsive to the output of the transform stage.

42. The processor of claim 39 further including a tracking filter responsive to the output of the transform stage.

43. The processor of claim 33 wherein the output of the tracking filter is a combination of the input signal and the feedback signal.

44. The processor of claim 33 wherein the output of the tracking filter is representative of a power estimate.

45. The processor of claim 45 wherein the power estimate is an intermediate power estimate.

47. The variable attack and release processor of claim 46 wherein the output of the tracking filter is a combination of the input signal and the feedback signal.

48. The variable attack and release processor of claim 46 wherein the output of the tracking filter is representative of a power estimate.

49. The variable attack and release processor of claim 48 wherein the power estimate signal is an intermediate power estimate.

50. The variable attack and release processor of claim 46 wherein the comparison signal is a variable.

51. The variable attack and release processor of claim 46 wherein the comparison signal is a logic signal.

52. The variable attack and release processor of claim 50 wherein a transform stage receives the comparison signal and provides a transform signal to the tracking filter.

53. The variable attack and release processor of claim 51 wherein a first stage receives the comparison signal and provides a first stage output to the tracking filter.

54. The variable attack and release processor of claim 46 wherein the comparison signal comprises both a variable and a logic signal.

55. The variable attack and release processor of claim 54 wherein a first stage receives the logic signal and provides a first stage output, and the transform stage receives the variable and the first stage output and provides a transform signal to the tracking filter.

56. The processor of claim 40 wherein the tracking filter comprises a plurality of tracking filters.

57. The processor of claim 41 wherein the tracking filter comprises a plurality of tracking filters.

58. The variable attack and release processor of claim 46 wherein the tracking filter comprises a plurality of tracking filters.

59. The variable attack and release processor of claim 53 further including a second stage responsive to at least one of a group comprising system parameter signal, user preference signal, feedback signal, and a characteristic of the input signal, for modifying the first stage output.

60. The variable attack and release processor of claim 55 further including a second stage responsive to at least one of a group comprising system parameter signal, user preference signal, feedback signal, and a characteristic of the input signal, for modifying the first stage output.

62. The signal processor system of claim 1 wherein the power estimation signal is a noise signal.

63. The variable attack and release processor of claim 13 wherein the input signal is a noise signal.

64. The variable attack and release processor of claim 46 wherein the input signal is a noise signal.

13. A variable attack and release processor having an output comprising

an input signal,

a feedback signal,

a comparison stage for providing as a comparison signal a comparison of the input signal and the feedback signal, and

a first stage for applying, in accordance with a first characteristic of the comparison signal, a first algorithm, and providing a first stage output signal in accordance therewith.

18. The variable attack and release processor where the first algorithm comprises a series of computer programming steps.

46. A variable attack and release processor having an output comprising

an input signal,

a feedback signal,

a comparison stage for providing as a comparison signal a comparison of the input signal and the feedback signal, and

a tracking filter responsive to an output of the comparison stage for producing an output in accordance therewith.

61. A signal processor comprising

a power estimation signal

a variable attack and release stage for detecting changes in amplitude of the power estimation signal relative to time,

comparing the changes in amplitude relative to time to a first predetermined threshold,

applying a first correction factor if the change in amplitude does not exceed the first predetermined threshold,

applying a second correction factor if the change in amplitude exceeds the first predetermined threshold.