Bottom gate thin film transistor, method of producing the transistor, and display device
First Claim
Patent Images
1. A method of producing a bottom gate thin film transistor, comprising the steps of:
- forming a gate electrode on an insulating substrate;
forming a gate insulating film over the gate electrode;
forming a first semiconductor thin film for a channel over the gate insulating film;
forming a second semiconductor thin film for a source and a drain over the first semiconductor thin film;
processing stacked layers of the first semiconductor thin film and the second semiconductor thin film so as to be formed into an island;
subsequent to the step of processing stacked layers, depositing a source/drain electrode metal over the stacked layers of the first semiconductor thin film and the second semiconductor thin film;
etching a region of the deposited source/drain electrode metal, the region being located above the channel, in the depth direction to expose the second semiconductor thin film, whereby a source electrode and a drain electrode are formed; and
etching away the exposed portion of the second semiconductor thin film in the depth direction with the use of a non-ionic excited species to form a channel.
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Abstract
In the production of channel etch type bottom gate thin film transistors, etching damage in a channel etch step is prevented to improve the transistor performance. The channel etch is performed using non-ionic excited species, such as hydrogen radicals and fluorine radicals, generated by contact-decomposition reaction which utilizes a metal heated by electric resistance heating. Alternatively, in place of the channel etch, a portion of the source/drain semiconductor thin film immediately above the channel is nitrided by a non-ionic nitrogen-containing decomposition product that is produced by contacting molecules of a chemical substance containing nitrogen atoms with a metal heated by electric resistance heating to decompose the chemical molecules.
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Citations
31 Claims
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1. A method of producing a bottom gate thin film transistor, comprising the steps of:
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forming a gate electrode on an insulating substrate;
forming a gate insulating film over the gate electrode;
forming a first semiconductor thin film for a channel over the gate insulating film;
forming a second semiconductor thin film for a source and a drain over the first semiconductor thin film;
processing stacked layers of the first semiconductor thin film and the second semiconductor thin film so as to be formed into an island;
subsequent to the step of processing stacked layers, depositing a source/drain electrode metal over the stacked layers of the first semiconductor thin film and the second semiconductor thin film;
etching a region of the deposited source/drain electrode metal, the region being located above the channel, in the depth direction to expose the second semiconductor thin film, whereby a source electrode and a drain electrode are formed; and
etching away the exposed portion of the second semiconductor thin film in the depth direction with the use of a non-ionic excited species to form a channel. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 19, 20, 21, 22, 23, 25, 26, 28, 29)
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18. A method of producing a bottom gate thin film transistor, comprising the steps of:
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forming a gate electrode on an insulating substrate;
forming a gate insulating film over the gate electrode;
forming a first semiconductor thin film for a channel over the gate insulating film;
forming a second semiconductor thin film for a source and a drain over the first semiconductor thin film;
processing stacked layers of the first semiconductor thin film and the second semiconductor thin film into an island;
subsequent to the step of processing stacked layers, depositing a source/drain electrode metal over the stacked layers;
etching a region of the deposited source/drain electrode metal, the region being located above the channel, in the depth direction to expose the second semiconductor thin film, whereby a source electrode and a drain electrode are formed; and
nitriding the exposed portion of the second semiconductor thin film using a non-ionic nitrogen-containing decomposition product that is produced by decomposing molecules of a chemical substance containing nitrogen atoms.
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24. A bottom gate thin film transistor comprising:
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a gate electrode formed on an insulating substrate;
a gate insulating film formed over the gate electrode;
a channel comprising a first semiconductor thin film stacked over the gate insulating film;
a source region and a drain region each comprising a second semiconductor thin film that is stacked over a region of the first semiconductor thin film exclusive of the channel;
a source electrode and a drain electrode formed on the second semiconductor thin film; and
a passivation film composed of a silicon nitride film formed on the channel;
wherein a portion of the channel contains at least one element selected from the group consisting of tungsten, tantalum, molybdenum, vanadium, platinum, and thorium, the portion of the channel being adjacent to a surface thereof which is in contact with the silicon nitride film; and
the total atomic density of the at least one element is in the range of from 1×
1016·
cm−
3 to 1×
1019 cm−
3. - View Dependent Claims (30, 31)
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27. A bottom gate thin film transistor comprising:
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a gate electrode formed on an insulating substrate;
a gate insulating film formed over the gate electrode;
a channel formed of a first semiconductor thin film stacked over the gate insulating film;
a source and a drain each formed of a second semiconductor thin film stacked over the first semiconductor thin film;
a nitrided region in which a portion of the second semiconductor thin film disposed immediately above the channel is nitrided; and
a source electrode and a drain electrode, each formed on a portion of the second semiconductor thin film exclusive of the nitrided region;
wherein a portion of the channel contains at least one element selected from the group consisting of tungsten, tantalum, molybdenum, vanadium, platinum, and thorium, the portion of the channel being adjacent to a surface thereof which faces the nitrided region; and
the total atomic density of the at least one element is in the range of from 1×
1016·
cm−
3 to 1×
1019·
cm−
3.
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Specification
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Current AssigneeMatsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
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Original AssigneeMatsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
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InventorsSakai, Masahiro, Terauchi, Masaharu
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Granted Patent
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Time in Patent OfficeDays
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Field of Search
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US Class Current438/197
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CPC Class CodesG02F 1/1368 in which the switching elem...H01L 21/3211 Nitridation of silicon-cont...H01L 21/32135 by vapour etching onlyH01L 21/67069 for drying etchingH01L 29/66765 Lateral single gate single ...H10K 59/12 Active-matrix OLED [AMOLED]...H10K 71/50 Forming devices by joining ...
