Integration of high voltage self-aligned MOS components

• US 20020055220A1
• Filed: 11/02/2001
• Published: 05/09/2002
• Est. Priority Date: 11/03/2000
• Status: Active Grant

• Current Assignee: Lantiq Beteiligungs-GmbH & Company KG (Intel Corporation)
• Original Assignee: Infineon Technologies AG
• Inventors: Soderbarg, Anders, Olofsson, Peter, Litwin, Andrej
• Granted Patent: US 6,686,233 B2
• Time in Patent Office: Days
• US Class Current: 438/234
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823857 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66681 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors

Abstract

The invention relates to a method for forming a high voltage NMOS transistor together with a low voltage NMOS transistor and a low voltage PMOS transistor, respectively, in an n-well CMOS process by adding solely two additional process steps to a conventional CMOS process: (i) a masking step, and (ii) an ion implantation step for forming a doped channel region for the high voltage MOS transistor in the substrate self-aligned to the edge of the high voltage MOS transistor gate region. The ion implantation is performed through the mask in a direction, which is inclined at an angle to the normal of the substrate surface, to thereby create the doped channel region partly underneath the gate region of the high voltage MOS transistor.

Claims

1. In an CMOS or BICMOS process a method for forming a high voltage NMOS transistor together with a low voltage NMOS transistor and a low voltage PMOS transistor, respectively, comprising the steps of:

providing a semiconductor substrate;

forming n-well regions for the high voltage NMOS transistor and the low voltage PMOS transistor in the substrate by means of ion implantation;

forming a p-well region for the low voltage NMOS transistor in the substrate by means of ion implantation;

forming isolation areas on top of and/or in the substrate to laterally separate the transistors from each other and to define a voltage-distributing region in the high voltage NMOS transistor;

producing gate regions for the high voltage NMOS transistor and the low voltage NMOS and PMOS transistors, respectively, by forming a respective thin gate oxide on the substrate;

depositing a layer of a conducting or semiconducting material thereon; and

patterning said layer to form the respective gate regions, whereby the gate region for the high voltage NMOS transistor is formed partly above the isolation area defining the voltage distributing region;

forming a p-doped channel region for the high voltage NMOS transistor in the substrate self-aligned to the edge of the high voltage NMOS transistor gate region;

forming source and drain regions for the low voltage PMOS transistor by means of creating ion implanted p⁺-regions; and

forming source and drain regions for the high voltage and low voltage NMOS transistors by means of creating ion implanted n⁺ regions, wherein the source region for the high voltage NMOS transistor is created within the p-doped channel region, wherein;

the step of forming a p-doped channel region for the high voltage NMOS transistor in the substrate self-aligned to the edge of the high voltage NMOS transistor gate region is performed by ion implantation through a mask, said ion implantation being effectuated in a direction, which is inclined at an angle to the normal of the substrate surface, to thereby create said p-doped channel region partly underneath the gate region of the high voltage NMOS transistor.

2. The method as claimed in claim 1 wherein said p-doped channel region for the high voltage NMOS transistor is created by ion implantation of boron, or other p-type dopant such as indium, aluminium, BF₂ or BF₃.

3. The method as claimed in claim 1 wherein said p-doped channel region for the high voltage NMOS transistor is created by ion implantation at a dose ranging from 10¹² cm⁻

2 to 10¹⁵ cm<sup>−

2</sup>.

4. The method as claimed in claim 1 wherein said p-doped channel region for the high voltage NMOS transistor is created by ion implantation at an energy between 10 keV and 1000 keV, and more preferably between 10 keV and 300 keV.

5. The method as claimed in claim 1 wherein the angle with which the implantation direction is inclined from normal incidence is within the range of 15-75°

.

6. The method as claimed in claim 1 wherein said p-doped channel region for the high voltage NMOS transistor is created by ion implantation at a dose and at an energy such that a controlled performance of the high voltage NMOS transistor is obtained.

7. The method as claimed in claim 1 wherein said p-doped channel region for the high voltage NMOS transistor is created by ion implantation through a mask and at an energy such that a dopant concentration is achieved underneath the gate region of the high voltage NMOS transistor which is at least as high as the dopant concentration outside the edge of the high voltage NMOS transistor gate region.

8. The method as claimed in claim 7 wherein said p-doped channel region for the high voltage NMOS transistor is created such that said channel region has the highest dopant concentration underneath the gate region of the high voltage NMOS transistor.

9. The method as claimed in claim 1 wherein said conducting or semiconducting material, of which the layer forming the gate region is made, is polysilicon.

10. The method as claimed in claim 1 wherein the layer, which forms the gate region, is made thick to prevent the dopant implanted during the step of forming the p-doped channel region for the high voltage NMOS transistor from penetrating through said gate region layer.

11. The method as claimed in claim 1 wherein the layer, which forms the gate region, is patterned using a gate region mask;

the mask used for ion implantation to form the p-doped channel region is arranged on top of the gate region mask; and

the ion implantation to form the p-doped channel region is performed through both of said masks.

12. The method as claimed in claim 1 wherein said p-doped channel region for the high voltage NMOS transistor is created by ion implantation in plurality of directions, each of which being inclined at said angle to the normal of the substrate surface.

13. The method as claimed in claim 12 wherein said plurality of implantation directions are four;

and wherein said directions are symmetrically distributed around the normal of the substrate surface.

14. The method as claimed in claim 12 wherein the high voltage NMOS transistor is symmetric with respect to at least one plane parallel to the normal of the substrate surface.

15. The method as claimed in claim 1 wherein said isolation areas are formed as LOCOS oxide.

16. The method as claimed in claim 1 wherein said isolation areas are formed as shallow trench isolation (STI) areas.

17. The method as claimed in claim 1 wherein the isolation area defining the voltage-distributing region within the high voltage NMOS transistor is a low-doped n³¹ region.

18. The method as claimed in claim 1 further comprising the formation of a high voltage PMOS transistor, wherein

a p-well region for the high voltage PMOS transistor is formed in the substrate simultaneously with the formation of the p-well region for the low voltage NMOS transistor;

an isolation area defining a voltage-distributing region in the high voltage PMOS transistor is formed simultaneously with the formation of said isolation areas;

a gate region for the high voltage PMOS transistor is produced simultaneously as the production of said gate regions for the high voltage NMOS transistor and the low voltage NMOS and PMOS transistors, respectively, whereby the gate region for the high voltage PMOS transistor is formed partly above the isolation area defining the voltage distributing region in the high voltage PMOS transistor;

and further comprising;

forming an n-doped channel region for the high voltage PMOS transistor in the substrate self-aligned to the edge of the high voltage PMOS transistor gate region, by means of ion implantation through a mask, said ion implantation being effectuated in a direction, which is inclined at an angle to the normal of the substrate surface, to thereby create said n-doped channel region partly underneath the gate region of the high voltage PMOS transistor; and

forming drain and source regions for the high voltage PMOS transistor by means of creating ion implanted p⁺ regions.

19. The method as claimed in claim 18 wherein the step of forming a p-well region for the high voltage PMOS transistor is preceded by the formation of a large n-doped region for the high voltage PMOS transistor;

and

wherein the p-well region for the high voltage PMOS transistor is formed within said n-doped region.

20. An integrated CMOS- or BiCMOS-based circuit comprising at least a high voltage NMOS transistor, a low voltage NMOS transistor and a low voltage PMOS transistor, respectively, wherein

said transistors are formed according to the method as claimed in claim 1.

21. In an CMOS or BiCMOS process a method for forming a high voltage PMOS transistor together with a low voltage NMOS transistor and a low voltage PMOS transistor, respectively, comprising the steps of:

providing a semiconductor substrate;

forming an n-well region for the low voltage PMOS transistor in the substrate by means of ion implantation;

forming p-well regions for the high voltage PMOS transistor and the low voltage NMOS transistor in the substrate by means of ion implantation;

forming isolation areas on top of and/or in the substrate to laterally separate the transistors from each other and to define a voltage-distributing region in the high voltage PMOS transistor;

producing gate regions for the high voltage PMOS transistor and the low voltage NMOS and PMOS transistors, respectively, by forming a respective thin gate oxide on the substrate;

depositing a layer of a conducting or a semiconducting material thereon; and

patterning said layer to form the respective gate regions, whereby the gate region for the high voltage PMOS transistor is formed partly above the isolation area defining the voltage distributing region;

forming an n-doped channel region for the high voltage PMOS transistor in the substrate self-aligned to the edge of the high voltage PMOS transistor gate region;

forming drain and source regions for the high and low voltage PMOS transistors by means of creating ion implanted p⁺-regions, wherein the source region for the high voltage PMOS transistor is created within the n-doped channel region,; and

forming drain and source regions for the low voltage NMOS transistor by means of creating ion implanted n⁺-well regions,

wherein;

the step of forming an n-doped channel region for the high voltage PMOS transistor in the substrate self-aligned to the edge of the high voltage PMOS transistor gate region is performed by ion implantation through a mask, said ion implantation being effectuated in a direction, which is inclined at an angle to the normal of the substrate surface, to thereby create said n-doped channel region partly underneath the gate region of the high voltage PMOS transistor.

22. The method as claimed in claim 21 wherein the step of forming a p-well region for the high voltage PMOS transistor is preceded by the formation of a large n-doped region for the high voltage PMOS transistor;

and wherein the p-well region for the high voltage PMOS transistor is formed within said n-doped region.

23. An integrated CMOS- or BiCMOS-based circuit comprising at least a high voltage PMOS transistor, a low voltage NMOS transistor and a low voltage PMOS transistor, respectively, wherein

said transistors are formed according to the method as claimed in claim 21.

25. The method as claimed in claim 24 wherein said p-doped channel region for the high voltage NMOS transistor is created by ion implantation at a dose ranging from 10¹² cm⁻

2 to 10¹⁵ cm<sup>−

2</sup>.

26. The method as claimed in claim 24 wherein said p-doped channel region for the high voltage NMOS transistor is created by ion implantation at an energy between 10 keV and 1000 keV, and more preferably between 10 keV and 300 keV.

27. The method as claimed in claim 24 wherein the angle with which the implantation direction is inclined from normal incidence is within the range of 15-75°

.

28. The method as claimed in claim 24 wherein said p-doped channel region for the high voltage NMOS transistor is created by ion implantation through a mask and at an energy such that a dopant concentration is achieved underneath the gate region of the high voltage NMOS transistor which is at least as high as the dopant concentration outside the edge of the high voltage NMOS transistor gate region.

29. The method as claimed in claim 28 wherein said p-doped channel region for the high voltage NMOS transistor is created such that said channel region has the highest dopant concentration underneath the gate region of the high voltage NMOS transistor.

30. The method as claimed in claim 24 wherein the layer, which forms the gate region, is made thick to prevent the dopant implanted during the step of forming the p-doped channel region for the high voltage NMOS transistor from penetrating through said gate region layer.

31. The method as claimed in claim 24 wherein the layer, which forms the gate region, is patterned using a gate region mask;

the mask used for ion implantation to form the p-doped channel region is arranged on top of the gate region mask; and

the ion implantation to form the p-doped channel region is performed through both of said masks.

32. The method as claimed in claim 24 wherein said p-doped channel region for the high voltage NMOS transistor is created by ion implantation in plurality of directions, each of which being inclined at said angle to the normal of the substrate surface.

24. In a MOS process a method for forming a high voltage NMOS transistor together with a low voltage NMOS transistor comprising the steps of:

providing a semiconductor substrate;

forming n-well regions for the high voltage NMOS transistor in the substrate by means of ion implantation;

forming a p-well region for the low voltage NMOS transistor in the substrate by means of ion implantation;

forming isolation areas on top of and/or in the substrate to laterally separate the transistors from each other and to define a voltage-distributing region in the high voltage NMOS transistor;

producing gate regions for the high voltage NMOS transistor and the low voltage NMOS transistors, respectively, by forming a respective thin gate oxide on the substrate;

depositing a layer of a conducting or semiconducting material thereon; and

patterning said layer to form the respective gate regions, whereby the gate region for the high voltage NMOS transistor is formed partly above the isolation area defining the voltage distributing region;

forming a p-doped channel region for the high voltage NMOS transistor in the substrate self-aligned to the edge of the high voltage NMOS transistor gate region; and

forming source and drain regions for the high voltage and low voltage NMOS transistors by means of creating ion implanted n+regions, wherein the source region for the high voltage NMOS transistor is created within the p-doped channel region,

wherein;

the step of forming a p-doped channel region for the high voltage NMOS transistor in the substrate self-aligned to the edge of the high voltage NMOS transistor gate region is performed by ion implantation through a mask, said ion implantation being effectuated in a direction, which is inclined at an angle to the normal of the substrate surface, to thereby create said p-doped channel region partly underneath the gate region of the high voltage NMOS transistor.