Semiconductor trench device with enhanced gate oxide integrity structure

• US 20020061623A1
• Filed: 11/20/2001
• Published: 05/23/2002
• Est. Priority Date: 06/16/2000
• Status: Active Grant

• Current Assignee: General Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Original Assignee: General Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Inventors: Hshieh, Fwu-Iuan, So, Koon Chong, Tsui, Yan Man
• Granted Patent: US 6,620,691 B2
• Time in Patent Office: Days
• US Class Current: 438/268
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A method for making trench DMOS is provided that improves the breakdown voltage of the oxide layer in a device having at least a first trench disposed in the active region of the device and a second trench disposed in the termination region of the device. In accordance with the method, mask techniques are used to thicken the oxide layer in the vicinity of the top corner of the second trench, thereby compensating for the thinning of this region (and the accompanying reduction in breakdown voltage) that occurs due to the two-dimensional oxidation during the manufacturing process.

Claims

1. A method for making a trench DMOS, comprising the steps of:

providing an article comprising a first region having a first conductivity type and a second region having a second conductivity type, the article having first and second trenches which are in communication with the first and second regions;

depositing a first electrically insulating layer over the surface of the first trench, the first insulating layer having a mean thickness over the first trench of t₁; and

depositing a second electrically insulating layer over the surface of the second trench, said second insulating layer having a mean thickness over the second trench of t₂,

wherein the ratio t₁/t₂ is at least about 1.2.

2. The method of claim 1, wherein t₁/t₂ is at least about 1.5.

3. The method of claim 1, wherein t₁/t₂ is at least about 2.

4. The method of claim 1, wherein t₁ is within the range of about 600 to about 840 angstroms.

5. The method of claim 1, wherein t₁ is within the range of about 750 to about 1050 angstroms.

6. The method of claim 1, wherein t₁ is within the range of about 1000 to about 1400 angstroms.

7. The method of claim 1, wherein the first and second insulating layers are oxide layers.

8. The method of claim 7, wherein the first and second insulating layers comprise silicon oxide.

9. The method of claim 1, further comprising the step of depositing polycrystalline silicon into the first and second trenches.

10. The method of claim 1, wherein the first insulating layer has an essentially uniform thickness over the first trench.

11. The method of claim 1, wherein the first insulating layer extends over at least a first locus defined by the surface of the first trench and the areas adjacent thereto, and wherein the first insulating layer has an essentially uniform thickness over the first locus.

12. The method of claim 11, wherein the first locus is defined by the surface of the first trench and the area within k/2 angstroms of the first trench, and wherein k is the maximum width of the first trench.

13. The method of claim 1, wherein the second insulating layer extends over at least a second locus defined by the surface of the second trench and the areas adjacent thereto, and wherein the second insulating layer has an essentially uniform thickness t_f over a first portion of the second locus and an essentially uniform thickness t_s over a second portion of the second locus.

14. The method of claim 13, wherein the second locus is defined by the surface of the second trench and the areas within k/2 angstroms of the second trench, and wherein k is the maximum width of the second trench.

15. The method of claim 14, wherein the first portion of the locus is the bottom of the trench, and wherein t_f>

t_s.

16. The method of claim 15, wherein the ratio t_f/t_s is at least about 1.2.

17. The method of claim 15, wherein t_f/t_s is at least about 1.5.

18. The method of claim 15, wherein t_f/t_s is at least about 2.

19. The method of claim 1, wherein the first region comprises an n doped epitaxial layer, and wherein the second region is a p type diffusion layer.

20. The method of claim 19, wherein the article further comprises an n+ doped epitaxial layer, wherein the p type diffusion layer is disposed on a first side of the n doped epitaxial layer, and wherein the n+ doped layer is disposed on a second side of the n doped epitaxial layer.

21. A trench DMOS device made in accordance with claim 1, said trench DMOS device comprising an active portion and a termination portion, and wherein the first trench is disposed in the termination portion and the second trench is disposed in the active portion.

22. A power MOSFET made in accordance with the method of claim 21.

24. The method of claim 23, wherein t₃>

t₂.

25. The method of claim 23, wherein t₁/t₂ is at least about 1.5.

26. The method of claim 23, wherein t₁/t₂ is at least about 2.

27. The method of claim 23, wherein t₁ is within the range of about 600 to about 840 angstroms.

28. The method of claim 23, wherein t₁ is within the range of about 750 to about 1050 angstroms.

29. The method of claim 23, wherein t₁ is within the range of about 1000 to about 1400 angstroms.

30. The method of claim 23, wherein the electrically insulating layer has an essentially uniform thickness over the first locus.

31. The method of claim 30, wherein the electrically insulating layer has an essentially uniform thickness over the second locus.

32. The method of claim 23, wherein the electrically insulating layer has an essentially uniform thickness over the third locus.

33. The method of claim 23, wherein the first and second insulating layers are oxide layers.

34. The method of claim 33, wherein the first and second insulating layers comprise silicon oxide.

35. A trench DMOS device made in accordance with claim 23, said trench DMOS device comprising an active portion and a termination portion, and wherein the first trench is disposed in the termination portion and the second trench is disposed in the active portion.

36. A power MOSFET made in accordance with the method of claim 23.

37. The method of claim 23, wherein the first locus is defined by the surface of the first trench and the areas within k/2 angstroms of the first trench, and wherein k is the maximum width of the first trench.

38. The method of claim 23, wherein the second locus is defined by the surface of the second trench and the areas within k/2 angstroms of the second trench, and wherein k is the maximum width of the second trench.

39. The method of claim 37 or 38, wherein k≦

8000 angstroms.

23. A method for making a trench DMOS, comprising the steps of:

providing an article comprising a first region of a first conductivity type and a second region of a second conductivity type, the article having first and second trenches in communication with the first and second regions, wherein the first trench and the areas adjacent thereto define a first locus, wherein the second trench and the areas adjacent thereto, exclusive of the bottom of the second trench, define a second locus, and wherein the bottom of the second trench defines a third locus; and

depositing an electrically insulating layer over the first, second and third loci, wherein the electrically insulating layer has a mean thickness over the first locus of t₁, a mean thickness over the second locus of t₂, and a mean thickness over the third locus of t₃, and wherein t₁>

t₂.

40. A trench DMOS device, comprising:

a first region having a first conductivity type;

a second region having a second conductivity type;

a termination portion, comprising a first trench which is in communication with said first and second regions, said first trench having a first electrically insulating layer disposed on the surface thereof which has a mean thickness t₁; and

an active portion, comprising a second trench which is in communication with said first and second regions, said second trench having a second electrically insulating layer disposed on the surface thereof which has a mean thickness t₂, wherein t₁>

t₂.

41. The device of claim 40, wherein t₁/t₂ is at least about 1.2.

42. The device of claim 40, wherein t₁/t₂ is at least about 1.5.

43. The device of claim 40, wherein t₁/t₂ is at least about 2.

44. The device of claim 40, wherein t₁ has a thickness within the range of 600 angstroms to about 840 angstroms.

45. The device of claim 40, wherein t₁ has a thickness within the range of 750 angstroms to about 1050 angstroms.

46. The device of claim 40, wherein t₁ has a thickness within the range of 1000 angstroms to about 1400 angstroms.

47. The device of claim 40, wherein the electrically insulating layer has an essentially uniform thickness over a first locus defined by the surface of the first trench and an area within k/2 angstroms of the first trench, and wherein k is the maximum width of the first trench.

48. The device of claim 40, wherein the electrically insulating layer has an essentially uniform thickness over a second locus defined by the surface of the second trench, exclusive of the bottom of the second trench, and an area within k/2 angstroms of the second trench, and wherein k is the maximum width of the second trench.

49. The device of claim 47 or 48, wherein k≦

8000 angstroms.

50. The device of claim 40, wherein the electrically insulating layer has an essentially uniform thickness over a third locus defined by the bottom of the second trench.

51. The device of claim 40, wherein the first and second insulating layers are oxide layers.

52. The device of claim 51, wherein the first and second insulating layers comprise silicon oxide.

53. A power MOSFET, comprising:

a first region having a first conductivity type;

a second region having a second conductivity type;

a termination portion, comprising a first trench which is in communication with said first and second regions;

a first oxide layer of essentially uniform thickness which extends over a first locus defined by the surface of said first trench and an area within k/2 angstroms of said first trench, wherein k is the maximum width of said first trench;

an active portion, comprising a second trench which is in communication with said first and second regions; and

a second oxide layer of essentially uniform thickness which extends over a second locus defined by the sides of said second trench and an area within k/2 angstroms of said second trench;

wherein the first oxide layer has a mean thickness t₁, wherein the second oxide layer has a mean thickness t₂, and wherein t₁>

t₂.

54. The power MOSFET of claim 53, wherein said second locus also includes the bottom of said second trench.

55. The power MOSFET of claim 53, further comprising a third electrically insulating layer of essentially uniform thickness which extends over a third locus defined by the bottom of said second trench.

56. The power MOSFET of claim 55, wherein said third electrically insulating layer has a mean thickness t₃, and wherein t₃>

t₂.

57. The power MOSFET of claim 53, wherein said first and second electrically insulating layers are oxide layers.

58. The power MOSFET of claim 57, wherein said first and second electrically insulating layers are silicon oxide layers.

59. The power MOSFET of claim 53, wherein k≦

8000 angstroms.

60. The power MOSFET of claim 53, wherein k≦

10000 angstroms.

61. A method for making a trench DMOS device, comprising the steps of:

providing an article comprising a first region of a first conductivity type and a second region of a second conductivity type, the article having first and second trenches which are in communication with the first and second regions;

depositing a first insulating layer over the surfaces of the first and second trenches, the first insulating layer having an mean thickness t₁;

depositing at least one mask over at least a portion of the insulating layer, thereby defining a masked region and an unmasked region, wherein the masked region extends over the surface of the first trench, and wherein the unmasked region extends over at least a portion of the surface of the second trench; and

depositing a second insulating layer over the unmasked region, said second insulating layer having an mean thickness t₂;

wherein k is the larger of t₁ and t₂, wherein m is the smaller of t₁ and t₂, and wherein k/m is at least about 1.2.

62. The method of claim 61, wherein the first insulating layer is removed from the unmasked region prior to deposition of the second insulating layer.

63. The method of claim 62, wherein the first insulating layer is removed by etching.

64. The method of claim 61, wherein the first and second insulating layers are oxide layers, and wherein the at least one mask is an oxide mask.

65. The method of claim 64, wherein the first and second insulating layers comprise silicon oxide.

66. The method of claim 64, wherein k/m is at least about 1.5.

67. The method of claim 64, wherein k/m is at least about 2.

68. The method of claim 61, wherein the unmasked region extends over a first portion of the surface of the second trench, and wherein the masked region extends over a second portion of the surface of the second trench.

69. The method of claim 68, wherein the unmasked region extends over the upper portion of the second trench, and wherein the masked region extends over the lower portion of the second trench.

70. The method of claim 61, wherein the unmasked region extends over the entire surface of the second trench.

71. An article, comprising:

a first region of a first conductivity type;

a second region of a second conductivity type;

a first trench, in communication with said first and second regions, said first trench terminating in a first bottom and having first and second walls, said first wall extending from said first bottom to a surface of the article, the intersection of said first wall and said surface defining a first locus;

a second trench, in communication with said first and second regions, said second trench having third and fourth walls and terminating in a second bottom, said second bottom defining a second locus;

an electrically insulating material disposed over said first locus; and

at least one mask defining a masked region and an unmasked region, said masked region extending over said first locus, and said unmasked region extending over at least a portion of said third and fourth walls.

72. The article of claim 71, wherein said masked region extends over said first trench and said unmasked region extends over said second trench.

73. The article of claim 71, wherein said masked region also extends over said second locus.

74. The article of claim 73, wherein said insulating material extends over said masked region.

75. The article of claim 74, wherein said insulating material does not extend over said unmasked region.

76. The article of claim 71, wherein said insulating material is disposed between said at least one mask and said first locus.

77. The article of claim 76, wherein said insulating material is disposed between said at least one mask and said second locus.

78. The article of claim 71, wherein said insulating material is a silicon oxide.

79. The article of claim 78, wherein said at least one mask is an oxide mask.

80. The article of claim 71, wherein said second region is a diffusion region.

81. The article of claim 72, wherein said diffusion region is a p type diffusion region.

82. A method for making a trench DMOS, comprising the steps of:

providing a substrate comprising a first region having a first conductivity type and a second region having a second conductivity type;

creating a first oxide layer on a surface of the substrate, the first oxide layer having first and second openings therein;

creating first and second trenches in the location of the first and second openings, respectively, the first and second trenches being in communication with the first and second regions;

creating a second oxide layer on the surface of the second trench, said second oxide layer having a mean thickness over the second trench of t₂; and

creating a third oxide layer on the surface of the first trench, said third oxide layer having a mean thickness over a first portion of the first trench of t₃ and having a mean thickness over a second portion of the first trench of t₄, wherein the ratio t₂/t₃ is at least about 1.2.

83. The method of claim 82, wherein the step of creating the first oxide layer includes the step of depositing a layer of oxide by vapor deposition.

84. The method of claim 82, wherein the step of creating the second oxide layer is preceded by the steps of:

depositing a sacrificial oxide layer on the surface of the second trench; and

removing the sacrificial oxide layer from the surface of the second trench.

85. The method of claim 82, wherein the step of creating the third oxide layer is preceded by the steps of:

disposing a second oxide layer over the surfaces of the first and second trenches;

placing an oxide mask over the second trench; and

removing the second oxide layer from the surface of the first trench.

86. The method of claim 85, wherein the step of creating the third oxide layer includes the step of depositing a layer of oxide by vapor deposition.

87. The method of claim 82, wherein the first oxide layer has a mean thickness of t₁, and wherein t₁/t₂>

1.

88. The method of claim 82, wherein t₃ and t₄ are essentially equal.

89. The method of claim 82, wherein t₃/t₄ is at least about 1.2.

90. The method of claim 89, wherein the second portion of the first trench includes the bottom of the first trench.

91. A MOSFET made in accordance with the method of claim 82, said MOSFET having an active region and a termination region, wherein the first trench is disposed in the active region and the second trench is disposed in the termination region.